1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * linux/arch/arm/vfp/vfpinstr.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2004 ARM Limited. 6*4882a593Smuzhiyun * Written by Deep Blue Solutions Limited. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * VFP instruction masks. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun #define INST_CPRTDO(inst) (((inst) & 0x0f000000) == 0x0e000000) 11*4882a593Smuzhiyun #define INST_CPRT(inst) ((inst) & (1 << 4)) 12*4882a593Smuzhiyun #define INST_CPRT_L(inst) ((inst) & (1 << 20)) 13*4882a593Smuzhiyun #define INST_CPRT_Rd(inst) (((inst) & (15 << 12)) >> 12) 14*4882a593Smuzhiyun #define INST_CPRT_OP(inst) (((inst) >> 21) & 7) 15*4882a593Smuzhiyun #define INST_CPNUM(inst) ((inst) & 0xf00) 16*4882a593Smuzhiyun #define CPNUM(cp) ((cp) << 8) 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define FOP_MASK (0x00b00040) 19*4882a593Smuzhiyun #define FOP_FMAC (0x00000000) 20*4882a593Smuzhiyun #define FOP_FNMAC (0x00000040) 21*4882a593Smuzhiyun #define FOP_FMSC (0x00100000) 22*4882a593Smuzhiyun #define FOP_FNMSC (0x00100040) 23*4882a593Smuzhiyun #define FOP_FMUL (0x00200000) 24*4882a593Smuzhiyun #define FOP_FNMUL (0x00200040) 25*4882a593Smuzhiyun #define FOP_FADD (0x00300000) 26*4882a593Smuzhiyun #define FOP_FSUB (0x00300040) 27*4882a593Smuzhiyun #define FOP_FDIV (0x00800000) 28*4882a593Smuzhiyun #define FOP_EXT (0x00b00040) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define FOP_TO_IDX(inst) ((inst & 0x00b00000) >> 20 | (inst & (1 << 6)) >> 4) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define FEXT_MASK (0x000f0080) 33*4882a593Smuzhiyun #define FEXT_FCPY (0x00000000) 34*4882a593Smuzhiyun #define FEXT_FABS (0x00000080) 35*4882a593Smuzhiyun #define FEXT_FNEG (0x00010000) 36*4882a593Smuzhiyun #define FEXT_FSQRT (0x00010080) 37*4882a593Smuzhiyun #define FEXT_FCMP (0x00040000) 38*4882a593Smuzhiyun #define FEXT_FCMPE (0x00040080) 39*4882a593Smuzhiyun #define FEXT_FCMPZ (0x00050000) 40*4882a593Smuzhiyun #define FEXT_FCMPEZ (0x00050080) 41*4882a593Smuzhiyun #define FEXT_FCVT (0x00070080) 42*4882a593Smuzhiyun #define FEXT_FUITO (0x00080000) 43*4882a593Smuzhiyun #define FEXT_FSITO (0x00080080) 44*4882a593Smuzhiyun #define FEXT_FTOUI (0x000c0000) 45*4882a593Smuzhiyun #define FEXT_FTOUIZ (0x000c0080) 46*4882a593Smuzhiyun #define FEXT_FTOSI (0x000d0000) 47*4882a593Smuzhiyun #define FEXT_FTOSIZ (0x000d0080) 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define FEXT_TO_IDX(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define vfp_get_sd(inst) ((inst & 0x0000f000) >> 11 | (inst & (1 << 22)) >> 22) 52*4882a593Smuzhiyun #define vfp_get_dd(inst) ((inst & 0x0000f000) >> 12 | (inst & (1 << 22)) >> 18) 53*4882a593Smuzhiyun #define vfp_get_sm(inst) ((inst & 0x0000000f) << 1 | (inst & (1 << 5)) >> 5) 54*4882a593Smuzhiyun #define vfp_get_dm(inst) ((inst & 0x0000000f) | (inst & (1 << 5)) >> 1) 55*4882a593Smuzhiyun #define vfp_get_sn(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7) 56*4882a593Smuzhiyun #define vfp_get_dn(inst) ((inst & 0x000f0000) >> 16 | (inst & (1 << 7)) >> 3) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define vfp_single(inst) (((inst) & 0x0000f00) == 0xa00) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define FPSCR_N (1 << 31) 61*4882a593Smuzhiyun #define FPSCR_Z (1 << 30) 62*4882a593Smuzhiyun #define FPSCR_C (1 << 29) 63*4882a593Smuzhiyun #define FPSCR_V (1 << 28) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #ifdef CONFIG_AS_VFP_VMRS_FPINST 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define fmrx(_vfp_) ({ \ 68*4882a593Smuzhiyun u32 __v; \ 69*4882a593Smuzhiyun asm(".fpu vfpv2\n" \ 70*4882a593Smuzhiyun "vmrs %0, " #_vfp_ \ 71*4882a593Smuzhiyun : "=r" (__v) : : "cc"); \ 72*4882a593Smuzhiyun __v; \ 73*4882a593Smuzhiyun }) 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define fmxr(_vfp_,_var_) \ 76*4882a593Smuzhiyun asm(".fpu vfpv2\n" \ 77*4882a593Smuzhiyun "vmsr " #_vfp_ ", %0" \ 78*4882a593Smuzhiyun : : "r" (_var_) : "cc") 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #else 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define vfpreg(_vfp_) #_vfp_ 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #define fmrx(_vfp_) ({ \ 85*4882a593Smuzhiyun u32 __v; \ 86*4882a593Smuzhiyun asm("mrc p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmrx %0, " #_vfp_ \ 87*4882a593Smuzhiyun : "=r" (__v) : : "cc"); \ 88*4882a593Smuzhiyun __v; \ 89*4882a593Smuzhiyun }) 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #define fmxr(_vfp_,_var_) \ 92*4882a593Smuzhiyun asm("mcr p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmxr " #_vfp_ ", %0" \ 93*4882a593Smuzhiyun : : "r" (_var_) : "cc") 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #endif 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun u32 vfp_single_cpdo(u32 inst, u32 fpscr); 98*4882a593Smuzhiyun u32 vfp_single_cprt(u32 inst, u32 fpscr, struct pt_regs *regs); 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun u32 vfp_double_cpdo(u32 inst, u32 fpscr); 101