1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * arch/arm/probes/kprobes/checkers-arm.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2014 Huawei Inc.
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/kernel.h>
9*4882a593Smuzhiyun #include "../decode.h"
10*4882a593Smuzhiyun #include "../decode-arm.h"
11*4882a593Smuzhiyun #include "checkers.h"
12*4882a593Smuzhiyun
arm_check_stack(probes_opcode_t insn,struct arch_probes_insn * asi,const struct decode_header * h)13*4882a593Smuzhiyun static enum probes_insn __kprobes arm_check_stack(probes_opcode_t insn,
14*4882a593Smuzhiyun struct arch_probes_insn *asi,
15*4882a593Smuzhiyun const struct decode_header *h)
16*4882a593Smuzhiyun {
17*4882a593Smuzhiyun /*
18*4882a593Smuzhiyun * PROBES_LDRSTRD, PROBES_LDMSTM, PROBES_STORE,
19*4882a593Smuzhiyun * PROBES_STORE_EXTRA may get here. Simply mark all normal
20*4882a593Smuzhiyun * insns as STACK_USE_NONE.
21*4882a593Smuzhiyun */
22*4882a593Smuzhiyun static const union decode_item table[] = {
23*4882a593Smuzhiyun /*
24*4882a593Smuzhiyun * 'STR{,D,B,H}, Rt, [Rn, Rm]' should be marked as UNKNOWN
25*4882a593Smuzhiyun * if Rn or Rm is SP.
26*4882a593Smuzhiyun * x
27*4882a593Smuzhiyun * STR (register) cccc 011x x0x0 xxxx xxxx xxxx xxxx xxxx
28*4882a593Smuzhiyun * STRB (register) cccc 011x x1x0 xxxx xxxx xxxx xxxx xxxx
29*4882a593Smuzhiyun */
30*4882a593Smuzhiyun DECODE_OR (0x0e10000f, 0x0600000d),
31*4882a593Smuzhiyun DECODE_OR (0x0e1f0000, 0x060d0000),
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /*
34*4882a593Smuzhiyun * x
35*4882a593Smuzhiyun * STRD (register) cccc 000x x0x0 xxxx xxxx xxxx 1111 xxxx
36*4882a593Smuzhiyun * STRH (register) cccc 000x x0x0 xxxx xxxx xxxx 1011 xxxx
37*4882a593Smuzhiyun */
38*4882a593Smuzhiyun DECODE_OR (0x0e5000bf, 0x000000bd),
39*4882a593Smuzhiyun DECODE_CUSTOM (0x0e5f00b0, 0x000d00b0, STACK_USE_UNKNOWN),
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /*
42*4882a593Smuzhiyun * For PROBES_LDMSTM, only stmdx sp, [...] need to examine
43*4882a593Smuzhiyun *
44*4882a593Smuzhiyun * Bit B/A (bit 24) encodes arithmetic operation order. 1 means
45*4882a593Smuzhiyun * before, 0 means after.
46*4882a593Smuzhiyun * Bit I/D (bit 23) encodes arithmetic operation. 1 means
47*4882a593Smuzhiyun * increment, 0 means decrement.
48*4882a593Smuzhiyun *
49*4882a593Smuzhiyun * So:
50*4882a593Smuzhiyun * B I
51*4882a593Smuzhiyun * / /
52*4882a593Smuzhiyun * A D | Rn |
53*4882a593Smuzhiyun * STMDX SP, [...] cccc 100x 00x0 xxxx xxxx xxxx xxxx xxxx
54*4882a593Smuzhiyun */
55*4882a593Smuzhiyun DECODE_CUSTOM (0x0edf0000, 0x080d0000, STACK_USE_STMDX),
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun /* P U W | Rn | Rt | imm12 |*/
58*4882a593Smuzhiyun /* STR (immediate) cccc 010x x0x0 1101 xxxx xxxx xxxx xxxx */
59*4882a593Smuzhiyun /* STRB (immediate) cccc 010x x1x0 1101 xxxx xxxx xxxx xxxx */
60*4882a593Smuzhiyun /* P U W | Rn | Rt |imm4| |imm4|*/
61*4882a593Smuzhiyun /* STRD (immediate) cccc 000x x1x0 1101 xxxx xxxx 1111 xxxx */
62*4882a593Smuzhiyun /* STRH (immediate) cccc 000x x1x0 1101 xxxx xxxx 1011 xxxx */
63*4882a593Smuzhiyun /*
64*4882a593Smuzhiyun * index = (P == '1'); add = (U == '1').
65*4882a593Smuzhiyun * Above insns with:
66*4882a593Smuzhiyun * index == 0 (str{,d,h} rx, [sp], #+/-imm) or
67*4882a593Smuzhiyun * add == 1 (str{,d,h} rx, [sp, #+<imm>])
68*4882a593Smuzhiyun * should be STACK_USE_NONE.
69*4882a593Smuzhiyun * Only str{,b,d,h} rx,[sp,#-n] (P == 1 and U == 0) are
70*4882a593Smuzhiyun * required to be examined.
71*4882a593Smuzhiyun */
72*4882a593Smuzhiyun /* STR{,B} Rt,[SP,#-n] cccc 0101 0xx0 1101 xxxx xxxx xxxx xxxx */
73*4882a593Smuzhiyun DECODE_CUSTOM (0x0f9f0000, 0x050d0000, STACK_USE_FIXED_XXX),
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /* STR{D,H} Rt,[SP,#-n] cccc 0001 01x0 1101 xxxx xxxx 1x11 xxxx */
76*4882a593Smuzhiyun DECODE_CUSTOM (0x0fdf00b0, 0x014d00b0, STACK_USE_FIXED_X0X),
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /* fall through */
79*4882a593Smuzhiyun DECODE_CUSTOM (0, 0, STACK_USE_NONE),
80*4882a593Smuzhiyun DECODE_END
81*4882a593Smuzhiyun };
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun return probes_decode_insn(insn, asi, table, false, false, stack_check_actions, NULL);
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun const struct decode_checker arm_stack_checker[NUM_PROBES_ARM_ACTIONS] = {
87*4882a593Smuzhiyun [PROBES_LDRSTRD] = {.checker = arm_check_stack},
88*4882a593Smuzhiyun [PROBES_STORE_EXTRA] = {.checker = arm_check_stack},
89*4882a593Smuzhiyun [PROBES_STORE] = {.checker = arm_check_stack},
90*4882a593Smuzhiyun [PROBES_LDMSTM] = {.checker = arm_check_stack},
91*4882a593Smuzhiyun };
92*4882a593Smuzhiyun
arm_check_regs_nouse(probes_opcode_t insn,struct arch_probes_insn * asi,const struct decode_header * h)93*4882a593Smuzhiyun static enum probes_insn __kprobes arm_check_regs_nouse(probes_opcode_t insn,
94*4882a593Smuzhiyun struct arch_probes_insn *asi,
95*4882a593Smuzhiyun const struct decode_header *h)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun asi->register_usage_flags = 0;
98*4882a593Smuzhiyun return INSN_GOOD;
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun
arm_check_regs_normal(probes_opcode_t insn,struct arch_probes_insn * asi,const struct decode_header * h)101*4882a593Smuzhiyun static enum probes_insn arm_check_regs_normal(probes_opcode_t insn,
102*4882a593Smuzhiyun struct arch_probes_insn *asi,
103*4882a593Smuzhiyun const struct decode_header *h)
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun u32 regs = h->type_regs.bits >> DECODE_TYPE_BITS;
106*4882a593Smuzhiyun int i;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun asi->register_usage_flags = 0;
109*4882a593Smuzhiyun for (i = 0; i < 5; regs >>= 4, insn >>= 4, i++)
110*4882a593Smuzhiyun if (regs & 0xf)
111*4882a593Smuzhiyun asi->register_usage_flags |= 1 << (insn & 0xf);
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun return INSN_GOOD;
114*4882a593Smuzhiyun }
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun
arm_check_regs_ldmstm(probes_opcode_t insn,struct arch_probes_insn * asi,const struct decode_header * h)117*4882a593Smuzhiyun static enum probes_insn arm_check_regs_ldmstm(probes_opcode_t insn,
118*4882a593Smuzhiyun struct arch_probes_insn *asi,
119*4882a593Smuzhiyun const struct decode_header *h)
120*4882a593Smuzhiyun {
121*4882a593Smuzhiyun unsigned int reglist = insn & 0xffff;
122*4882a593Smuzhiyun unsigned int rn = (insn >> 16) & 0xf;
123*4882a593Smuzhiyun asi->register_usage_flags = reglist | (1 << rn);
124*4882a593Smuzhiyun return INSN_GOOD;
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun
arm_check_regs_mov_ip_sp(probes_opcode_t insn,struct arch_probes_insn * asi,const struct decode_header * h)127*4882a593Smuzhiyun static enum probes_insn arm_check_regs_mov_ip_sp(probes_opcode_t insn,
128*4882a593Smuzhiyun struct arch_probes_insn *asi,
129*4882a593Smuzhiyun const struct decode_header *h)
130*4882a593Smuzhiyun {
131*4882a593Smuzhiyun /* Instruction is 'mov ip, sp' i.e. 'mov r12, r13' */
132*4882a593Smuzhiyun asi->register_usage_flags = (1 << 12) | (1<< 13);
133*4882a593Smuzhiyun return INSN_GOOD;
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun /*
137*4882a593Smuzhiyun * | Rn |Rt/d| | Rm |
138*4882a593Smuzhiyun * LDRD (register) cccc 000x x0x0 xxxx xxxx xxxx 1101 xxxx
139*4882a593Smuzhiyun * STRD (register) cccc 000x x0x0 xxxx xxxx xxxx 1111 xxxx
140*4882a593Smuzhiyun * | Rn |Rt/d| |imm4L|
141*4882a593Smuzhiyun * LDRD (immediate) cccc 000x x1x0 xxxx xxxx xxxx 1101 xxxx
142*4882a593Smuzhiyun * STRD (immediate) cccc 000x x1x0 xxxx xxxx xxxx 1111 xxxx
143*4882a593Smuzhiyun *
144*4882a593Smuzhiyun * Such instructions access Rt/d and its next register, so different
145*4882a593Smuzhiyun * from others, a specific checker is required to handle this extra
146*4882a593Smuzhiyun * implicit register usage.
147*4882a593Smuzhiyun */
arm_check_regs_ldrdstrd(probes_opcode_t insn,struct arch_probes_insn * asi,const struct decode_header * h)148*4882a593Smuzhiyun static enum probes_insn arm_check_regs_ldrdstrd(probes_opcode_t insn,
149*4882a593Smuzhiyun struct arch_probes_insn *asi,
150*4882a593Smuzhiyun const struct decode_header *h)
151*4882a593Smuzhiyun {
152*4882a593Smuzhiyun int rdt = (insn >> 12) & 0xf;
153*4882a593Smuzhiyun arm_check_regs_normal(insn, asi, h);
154*4882a593Smuzhiyun asi->register_usage_flags |= 1 << (rdt + 1);
155*4882a593Smuzhiyun return INSN_GOOD;
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun const struct decode_checker arm_regs_checker[NUM_PROBES_ARM_ACTIONS] = {
160*4882a593Smuzhiyun [PROBES_MRS] = {.checker = arm_check_regs_normal},
161*4882a593Smuzhiyun [PROBES_SATURATING_ARITHMETIC] = {.checker = arm_check_regs_normal},
162*4882a593Smuzhiyun [PROBES_MUL1] = {.checker = arm_check_regs_normal},
163*4882a593Smuzhiyun [PROBES_MUL2] = {.checker = arm_check_regs_normal},
164*4882a593Smuzhiyun [PROBES_MUL_ADD_LONG] = {.checker = arm_check_regs_normal},
165*4882a593Smuzhiyun [PROBES_MUL_ADD] = {.checker = arm_check_regs_normal},
166*4882a593Smuzhiyun [PROBES_LOAD] = {.checker = arm_check_regs_normal},
167*4882a593Smuzhiyun [PROBES_LOAD_EXTRA] = {.checker = arm_check_regs_normal},
168*4882a593Smuzhiyun [PROBES_STORE] = {.checker = arm_check_regs_normal},
169*4882a593Smuzhiyun [PROBES_STORE_EXTRA] = {.checker = arm_check_regs_normal},
170*4882a593Smuzhiyun [PROBES_DATA_PROCESSING_REG] = {.checker = arm_check_regs_normal},
171*4882a593Smuzhiyun [PROBES_DATA_PROCESSING_IMM] = {.checker = arm_check_regs_normal},
172*4882a593Smuzhiyun [PROBES_SEV] = {.checker = arm_check_regs_nouse},
173*4882a593Smuzhiyun [PROBES_WFE] = {.checker = arm_check_regs_nouse},
174*4882a593Smuzhiyun [PROBES_SATURATE] = {.checker = arm_check_regs_normal},
175*4882a593Smuzhiyun [PROBES_REV] = {.checker = arm_check_regs_normal},
176*4882a593Smuzhiyun [PROBES_MMI] = {.checker = arm_check_regs_normal},
177*4882a593Smuzhiyun [PROBES_PACK] = {.checker = arm_check_regs_normal},
178*4882a593Smuzhiyun [PROBES_EXTEND] = {.checker = arm_check_regs_normal},
179*4882a593Smuzhiyun [PROBES_EXTEND_ADD] = {.checker = arm_check_regs_normal},
180*4882a593Smuzhiyun [PROBES_BITFIELD] = {.checker = arm_check_regs_normal},
181*4882a593Smuzhiyun [PROBES_LDMSTM] = {.checker = arm_check_regs_ldmstm},
182*4882a593Smuzhiyun [PROBES_MOV_IP_SP] = {.checker = arm_check_regs_mov_ip_sp},
183*4882a593Smuzhiyun [PROBES_LDRSTRD] = {.checker = arm_check_regs_ldrdstrd},
184*4882a593Smuzhiyun };
185