1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * linux/arch/arm/plat-versatile/platsmp.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2002 ARM Ltd.
6*4882a593Smuzhiyun * All Rights Reserved
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * This code is specific to the hardware found on ARM Realview and
9*4882a593Smuzhiyun * Versatile Express platforms where the CPUs are unable to be individually
10*4882a593Smuzhiyun * woken, and where there is no way to hot-unplug CPUs. Real platforms
11*4882a593Smuzhiyun * should not copy this code.
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun #include <linux/init.h>
14*4882a593Smuzhiyun #include <linux/errno.h>
15*4882a593Smuzhiyun #include <linux/delay.h>
16*4882a593Smuzhiyun #include <linux/device.h>
17*4882a593Smuzhiyun #include <linux/jiffies.h>
18*4882a593Smuzhiyun #include <linux/smp.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #include <asm/cacheflush.h>
21*4882a593Smuzhiyun #include <asm/smp_plat.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #include <plat/platsmp.h>
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /*
26*4882a593Smuzhiyun * versatile_cpu_release controls the release of CPUs from the holding
27*4882a593Smuzhiyun * pen in headsmp.S, which exists because we are not always able to
28*4882a593Smuzhiyun * control the release of individual CPUs from the board firmware.
29*4882a593Smuzhiyun * Production platforms do not need this.
30*4882a593Smuzhiyun */
31*4882a593Smuzhiyun volatile int versatile_cpu_release = -1;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /*
34*4882a593Smuzhiyun * Write versatile_cpu_release in a way that is guaranteed to be visible to
35*4882a593Smuzhiyun * all observers, irrespective of whether they're taking part in coherency
36*4882a593Smuzhiyun * or not. This is necessary for the hotplug code to work reliably.
37*4882a593Smuzhiyun */
versatile_write_cpu_release(int val)38*4882a593Smuzhiyun static void versatile_write_cpu_release(int val)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun versatile_cpu_release = val;
41*4882a593Smuzhiyun smp_wmb();
42*4882a593Smuzhiyun sync_cache_w(&versatile_cpu_release);
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun /*
46*4882a593Smuzhiyun * versatile_lock exists to avoid running the loops_per_jiffy delay loop
47*4882a593Smuzhiyun * calibrations on the secondary CPU while the requesting CPU is using
48*4882a593Smuzhiyun * the limited-bandwidth bus - which affects the calibration value.
49*4882a593Smuzhiyun * Production platforms do not need this.
50*4882a593Smuzhiyun */
51*4882a593Smuzhiyun static DEFINE_RAW_SPINLOCK(versatile_lock);
52*4882a593Smuzhiyun
versatile_secondary_init(unsigned int cpu)53*4882a593Smuzhiyun void versatile_secondary_init(unsigned int cpu)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun /*
56*4882a593Smuzhiyun * let the primary processor know we're out of the
57*4882a593Smuzhiyun * pen, then head off into the C entry point
58*4882a593Smuzhiyun */
59*4882a593Smuzhiyun versatile_write_cpu_release(-1);
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /*
62*4882a593Smuzhiyun * Synchronise with the boot thread.
63*4882a593Smuzhiyun */
64*4882a593Smuzhiyun raw_spin_lock(&versatile_lock);
65*4882a593Smuzhiyun raw_spin_unlock(&versatile_lock);
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
versatile_boot_secondary(unsigned int cpu,struct task_struct * idle)68*4882a593Smuzhiyun int versatile_boot_secondary(unsigned int cpu, struct task_struct *idle)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun unsigned long timeout;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun /*
73*4882a593Smuzhiyun * Set synchronisation state between this boot processor
74*4882a593Smuzhiyun * and the secondary one
75*4882a593Smuzhiyun */
76*4882a593Smuzhiyun raw_spin_lock(&versatile_lock);
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /*
79*4882a593Smuzhiyun * This is really belt and braces; we hold unintended secondary
80*4882a593Smuzhiyun * CPUs in the holding pen until we're ready for them. However,
81*4882a593Smuzhiyun * since we haven't sent them a soft interrupt, they shouldn't
82*4882a593Smuzhiyun * be there.
83*4882a593Smuzhiyun */
84*4882a593Smuzhiyun versatile_write_cpu_release(cpu_logical_map(cpu));
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun /*
87*4882a593Smuzhiyun * Send the secondary CPU a soft interrupt, thereby causing
88*4882a593Smuzhiyun * the boot monitor to read the system wide flags register,
89*4882a593Smuzhiyun * and branch to the address found there.
90*4882a593Smuzhiyun */
91*4882a593Smuzhiyun arch_send_wakeup_ipi_mask(cpumask_of(cpu));
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun timeout = jiffies + (1 * HZ);
94*4882a593Smuzhiyun while (time_before(jiffies, timeout)) {
95*4882a593Smuzhiyun smp_rmb();
96*4882a593Smuzhiyun if (versatile_cpu_release == -1)
97*4882a593Smuzhiyun break;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun udelay(10);
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun /*
103*4882a593Smuzhiyun * now the secondary core is starting up let it run its
104*4882a593Smuzhiyun * calibrations, then wait for it to finish
105*4882a593Smuzhiyun */
106*4882a593Smuzhiyun raw_spin_unlock(&versatile_lock);
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun return versatile_cpu_release != -1 ? -ENOSYS : 0;
109*4882a593Smuzhiyun }
110