xref: /OK3568_Linux_fs/kernel/arch/arm/plat-pxa/mfp.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * linux/arch/arm/plat-pxa/mfp.c
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  *   Multi-Function Pin Support
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Copyright (C) 2007 Marvell Internation Ltd.
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * 2007-08-21: eric miao <eric.miao@marvell.com>
10*4882a593Smuzhiyun  *             initial version
11*4882a593Smuzhiyun  */
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <linux/kernel.h>
15*4882a593Smuzhiyun #include <linux/init.h>
16*4882a593Smuzhiyun #include <linux/io.h>
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #include <plat/mfp.h>
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #define MFPR_SIZE	(PAGE_SIZE)
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun /* MFPR register bit definitions */
23*4882a593Smuzhiyun #define MFPR_PULL_SEL		(0x1 << 15)
24*4882a593Smuzhiyun #define MFPR_PULLUP_EN		(0x1 << 14)
25*4882a593Smuzhiyun #define MFPR_PULLDOWN_EN	(0x1 << 13)
26*4882a593Smuzhiyun #define MFPR_SLEEP_SEL		(0x1 << 9)
27*4882a593Smuzhiyun #define MFPR_SLEEP_OE_N		(0x1 << 7)
28*4882a593Smuzhiyun #define MFPR_EDGE_CLEAR		(0x1 << 6)
29*4882a593Smuzhiyun #define MFPR_EDGE_FALL_EN	(0x1 << 5)
30*4882a593Smuzhiyun #define MFPR_EDGE_RISE_EN	(0x1 << 4)
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun #define MFPR_SLEEP_DATA(x)	((x) << 8)
33*4882a593Smuzhiyun #define MFPR_DRIVE(x)		(((x) & 0x7) << 10)
34*4882a593Smuzhiyun #define MFPR_AF_SEL(x)		(((x) & 0x7) << 0)
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun #define MFPR_EDGE_NONE		(0)
37*4882a593Smuzhiyun #define MFPR_EDGE_RISE		(MFPR_EDGE_RISE_EN)
38*4882a593Smuzhiyun #define MFPR_EDGE_FALL		(MFPR_EDGE_FALL_EN)
39*4882a593Smuzhiyun #define MFPR_EDGE_BOTH		(MFPR_EDGE_RISE | MFPR_EDGE_FALL)
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun /*
42*4882a593Smuzhiyun  * Table that determines the low power modes outputs, with actual settings
43*4882a593Smuzhiyun  * used in parentheses for don't-care values. Except for the float output,
44*4882a593Smuzhiyun  * the configured driven and pulled levels match, so if there is a need for
45*4882a593Smuzhiyun  * non-LPM pulled output, the same configuration could probably be used.
46*4882a593Smuzhiyun  *
47*4882a593Smuzhiyun  * Output value  sleep_oe_n  sleep_data  pullup_en  pulldown_en  pull_sel
48*4882a593Smuzhiyun  *                 (bit 7)    (bit 8)    (bit 14)     (bit 13)   (bit 15)
49*4882a593Smuzhiyun  *
50*4882a593Smuzhiyun  * Input            0          X(0)        X(0)        X(0)       0
51*4882a593Smuzhiyun  * Drive 0          0          0           0           X(1)       0
52*4882a593Smuzhiyun  * Drive 1          0          1           X(1)        0	  0
53*4882a593Smuzhiyun  * Pull hi (1)      1          X(1)        1           0	  0
54*4882a593Smuzhiyun  * Pull lo (0)      1          X(0)        0           1	  0
55*4882a593Smuzhiyun  * Z (float)        1          X(0)        0           0	  0
56*4882a593Smuzhiyun  */
57*4882a593Smuzhiyun #define MFPR_LPM_INPUT		(0)
58*4882a593Smuzhiyun #define MFPR_LPM_DRIVE_LOW	(MFPR_SLEEP_DATA(0) | MFPR_PULLDOWN_EN)
59*4882a593Smuzhiyun #define MFPR_LPM_DRIVE_HIGH    	(MFPR_SLEEP_DATA(1) | MFPR_PULLUP_EN)
60*4882a593Smuzhiyun #define MFPR_LPM_PULL_LOW      	(MFPR_LPM_DRIVE_LOW  | MFPR_SLEEP_OE_N)
61*4882a593Smuzhiyun #define MFPR_LPM_PULL_HIGH     	(MFPR_LPM_DRIVE_HIGH | MFPR_SLEEP_OE_N)
62*4882a593Smuzhiyun #define MFPR_LPM_FLOAT         	(MFPR_SLEEP_OE_N)
63*4882a593Smuzhiyun #define MFPR_LPM_MASK		(0xe080)
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun /*
66*4882a593Smuzhiyun  * The pullup and pulldown state of the MFP pin at run mode is by default
67*4882a593Smuzhiyun  * determined by the selected alternate function. In case that some buggy
68*4882a593Smuzhiyun  * devices need to override this default behavior,  the definitions below
69*4882a593Smuzhiyun  * indicates the setting of corresponding MFPR bits
70*4882a593Smuzhiyun  *
71*4882a593Smuzhiyun  * Definition       pull_sel  pullup_en  pulldown_en
72*4882a593Smuzhiyun  * MFPR_PULL_NONE       0         0        0
73*4882a593Smuzhiyun  * MFPR_PULL_LOW        1         0        1
74*4882a593Smuzhiyun  * MFPR_PULL_HIGH       1         1        0
75*4882a593Smuzhiyun  * MFPR_PULL_BOTH       1         1        1
76*4882a593Smuzhiyun  * MFPR_PULL_FLOAT	1         0        0
77*4882a593Smuzhiyun  */
78*4882a593Smuzhiyun #define MFPR_PULL_NONE		(0)
79*4882a593Smuzhiyun #define MFPR_PULL_LOW		(MFPR_PULL_SEL | MFPR_PULLDOWN_EN)
80*4882a593Smuzhiyun #define MFPR_PULL_BOTH		(MFPR_PULL_LOW | MFPR_PULLUP_EN)
81*4882a593Smuzhiyun #define MFPR_PULL_HIGH		(MFPR_PULL_SEL | MFPR_PULLUP_EN)
82*4882a593Smuzhiyun #define MFPR_PULL_FLOAT		(MFPR_PULL_SEL)
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun /* mfp_spin_lock is used to ensure that MFP register configuration
85*4882a593Smuzhiyun  * (most likely a read-modify-write operation) is atomic, and that
86*4882a593Smuzhiyun  * mfp_table[] is consistent
87*4882a593Smuzhiyun  */
88*4882a593Smuzhiyun static DEFINE_SPINLOCK(mfp_spin_lock);
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun static void __iomem *mfpr_mmio_base;
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun struct mfp_pin {
93*4882a593Smuzhiyun 	unsigned long	config;		/* -1 for not configured */
94*4882a593Smuzhiyun 	unsigned long	mfpr_off;	/* MFPRxx Register offset */
95*4882a593Smuzhiyun 	unsigned long	mfpr_run;	/* Run-Mode Register Value */
96*4882a593Smuzhiyun 	unsigned long	mfpr_lpm;	/* Low Power Mode Register Value */
97*4882a593Smuzhiyun };
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun static struct mfp_pin mfp_table[MFP_PIN_MAX];
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun /* mapping of MFP_LPM_* definitions to MFPR_LPM_* register bits */
102*4882a593Smuzhiyun static const unsigned long mfpr_lpm[] = {
103*4882a593Smuzhiyun 	MFPR_LPM_INPUT,
104*4882a593Smuzhiyun 	MFPR_LPM_DRIVE_LOW,
105*4882a593Smuzhiyun 	MFPR_LPM_DRIVE_HIGH,
106*4882a593Smuzhiyun 	MFPR_LPM_PULL_LOW,
107*4882a593Smuzhiyun 	MFPR_LPM_PULL_HIGH,
108*4882a593Smuzhiyun 	MFPR_LPM_FLOAT,
109*4882a593Smuzhiyun 	MFPR_LPM_INPUT,
110*4882a593Smuzhiyun };
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun /* mapping of MFP_PULL_* definitions to MFPR_PULL_* register bits */
113*4882a593Smuzhiyun static const unsigned long mfpr_pull[] = {
114*4882a593Smuzhiyun 	MFPR_PULL_NONE,
115*4882a593Smuzhiyun 	MFPR_PULL_LOW,
116*4882a593Smuzhiyun 	MFPR_PULL_HIGH,
117*4882a593Smuzhiyun 	MFPR_PULL_BOTH,
118*4882a593Smuzhiyun 	MFPR_PULL_FLOAT,
119*4882a593Smuzhiyun };
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun /* mapping of MFP_LPM_EDGE_* definitions to MFPR_EDGE_* register bits */
122*4882a593Smuzhiyun static const unsigned long mfpr_edge[] = {
123*4882a593Smuzhiyun 	MFPR_EDGE_NONE,
124*4882a593Smuzhiyun 	MFPR_EDGE_RISE,
125*4882a593Smuzhiyun 	MFPR_EDGE_FALL,
126*4882a593Smuzhiyun 	MFPR_EDGE_BOTH,
127*4882a593Smuzhiyun };
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun #define mfpr_readl(off)			\
130*4882a593Smuzhiyun 	__raw_readl(mfpr_mmio_base + (off))
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun #define mfpr_writel(off, val)		\
133*4882a593Smuzhiyun 	__raw_writel(val, mfpr_mmio_base + (off))
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun #define mfp_configured(p)	((p)->config != -1)
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun /*
138*4882a593Smuzhiyun  * perform a read-back of any valid MFPR register to make sure the
139*4882a593Smuzhiyun  * previous writings are finished
140*4882a593Smuzhiyun  */
141*4882a593Smuzhiyun static unsigned long mfpr_off_readback;
142*4882a593Smuzhiyun #define mfpr_sync()	(void)__raw_readl(mfpr_mmio_base + mfpr_off_readback)
143*4882a593Smuzhiyun 
__mfp_config_run(struct mfp_pin * p)144*4882a593Smuzhiyun static inline void __mfp_config_run(struct mfp_pin *p)
145*4882a593Smuzhiyun {
146*4882a593Smuzhiyun 	if (mfp_configured(p))
147*4882a593Smuzhiyun 		mfpr_writel(p->mfpr_off, p->mfpr_run);
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun 
__mfp_config_lpm(struct mfp_pin * p)150*4882a593Smuzhiyun static inline void __mfp_config_lpm(struct mfp_pin *p)
151*4882a593Smuzhiyun {
152*4882a593Smuzhiyun 	if (mfp_configured(p)) {
153*4882a593Smuzhiyun 		unsigned long mfpr_clr = (p->mfpr_run & ~MFPR_EDGE_BOTH) | MFPR_EDGE_CLEAR;
154*4882a593Smuzhiyun 		if (mfpr_clr != p->mfpr_run)
155*4882a593Smuzhiyun 			mfpr_writel(p->mfpr_off, mfpr_clr);
156*4882a593Smuzhiyun 		if (p->mfpr_lpm != mfpr_clr)
157*4882a593Smuzhiyun 			mfpr_writel(p->mfpr_off, p->mfpr_lpm);
158*4882a593Smuzhiyun 	}
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun 
mfp_config(unsigned long * mfp_cfgs,int num)161*4882a593Smuzhiyun void mfp_config(unsigned long *mfp_cfgs, int num)
162*4882a593Smuzhiyun {
163*4882a593Smuzhiyun 	unsigned long flags;
164*4882a593Smuzhiyun 	int i;
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun 	spin_lock_irqsave(&mfp_spin_lock, flags);
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun 	for (i = 0; i < num; i++, mfp_cfgs++) {
169*4882a593Smuzhiyun 		unsigned long tmp, c = *mfp_cfgs;
170*4882a593Smuzhiyun 		struct mfp_pin *p;
171*4882a593Smuzhiyun 		int pin, af, drv, lpm, edge, pull;
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun 		pin = MFP_PIN(c);
174*4882a593Smuzhiyun 		BUG_ON(pin >= MFP_PIN_MAX);
175*4882a593Smuzhiyun 		p = &mfp_table[pin];
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 		af  = MFP_AF(c);
178*4882a593Smuzhiyun 		drv = MFP_DS(c);
179*4882a593Smuzhiyun 		lpm = MFP_LPM_STATE(c);
180*4882a593Smuzhiyun 		edge = MFP_LPM_EDGE(c);
181*4882a593Smuzhiyun 		pull = MFP_PULL(c);
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun 		/* run-mode pull settings will conflict with MFPR bits of
184*4882a593Smuzhiyun 		 * low power mode state,  calculate mfpr_run and mfpr_lpm
185*4882a593Smuzhiyun 		 * individually if pull != MFP_PULL_NONE
186*4882a593Smuzhiyun 		 */
187*4882a593Smuzhiyun 		tmp = MFPR_AF_SEL(af) | MFPR_DRIVE(drv);
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun 		if (likely(pull == MFP_PULL_NONE)) {
190*4882a593Smuzhiyun 			p->mfpr_run = tmp | mfpr_lpm[lpm] | mfpr_edge[edge];
191*4882a593Smuzhiyun 			p->mfpr_lpm = p->mfpr_run;
192*4882a593Smuzhiyun 		} else {
193*4882a593Smuzhiyun 			p->mfpr_lpm = tmp | mfpr_lpm[lpm] | mfpr_edge[edge];
194*4882a593Smuzhiyun 			p->mfpr_run = tmp | mfpr_pull[pull];
195*4882a593Smuzhiyun 		}
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun 		p->config = c; __mfp_config_run(p);
198*4882a593Smuzhiyun 	}
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 	mfpr_sync();
201*4882a593Smuzhiyun 	spin_unlock_irqrestore(&mfp_spin_lock, flags);
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun 
mfp_read(int mfp)204*4882a593Smuzhiyun unsigned long mfp_read(int mfp)
205*4882a593Smuzhiyun {
206*4882a593Smuzhiyun 	unsigned long val, flags;
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun 	BUG_ON(mfp < 0 || mfp >= MFP_PIN_MAX);
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun 	spin_lock_irqsave(&mfp_spin_lock, flags);
211*4882a593Smuzhiyun 	val = mfpr_readl(mfp_table[mfp].mfpr_off);
212*4882a593Smuzhiyun 	spin_unlock_irqrestore(&mfp_spin_lock, flags);
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun 	return val;
215*4882a593Smuzhiyun }
216*4882a593Smuzhiyun 
mfp_write(int mfp,unsigned long val)217*4882a593Smuzhiyun void mfp_write(int mfp, unsigned long val)
218*4882a593Smuzhiyun {
219*4882a593Smuzhiyun 	unsigned long flags;
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun 	BUG_ON(mfp < 0 || mfp >= MFP_PIN_MAX);
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun 	spin_lock_irqsave(&mfp_spin_lock, flags);
224*4882a593Smuzhiyun 	mfpr_writel(mfp_table[mfp].mfpr_off, val);
225*4882a593Smuzhiyun 	mfpr_sync();
226*4882a593Smuzhiyun 	spin_unlock_irqrestore(&mfp_spin_lock, flags);
227*4882a593Smuzhiyun }
228*4882a593Smuzhiyun 
mfp_init_base(void __iomem * mfpr_base)229*4882a593Smuzhiyun void __init mfp_init_base(void __iomem *mfpr_base)
230*4882a593Smuzhiyun {
231*4882a593Smuzhiyun 	int i;
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun 	/* initialize the table with default - unconfigured */
234*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(mfp_table); i++)
235*4882a593Smuzhiyun 		mfp_table[i].config = -1;
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun 	mfpr_mmio_base = mfpr_base;
238*4882a593Smuzhiyun }
239*4882a593Smuzhiyun 
mfp_init_addr(struct mfp_addr_map * map)240*4882a593Smuzhiyun void __init mfp_init_addr(struct mfp_addr_map *map)
241*4882a593Smuzhiyun {
242*4882a593Smuzhiyun 	struct mfp_addr_map *p;
243*4882a593Smuzhiyun 	unsigned long offset, flags;
244*4882a593Smuzhiyun 	int i;
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun 	spin_lock_irqsave(&mfp_spin_lock, flags);
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun 	/* mfp offset for readback */
249*4882a593Smuzhiyun 	mfpr_off_readback = map[0].offset;
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun 	for (p = map; p->start != MFP_PIN_INVALID; p++) {
252*4882a593Smuzhiyun 		offset = p->offset;
253*4882a593Smuzhiyun 		i = p->start;
254*4882a593Smuzhiyun 
255*4882a593Smuzhiyun 		do {
256*4882a593Smuzhiyun 			mfp_table[i].mfpr_off = offset;
257*4882a593Smuzhiyun 			mfp_table[i].mfpr_run = 0;
258*4882a593Smuzhiyun 			mfp_table[i].mfpr_lpm = 0;
259*4882a593Smuzhiyun 			offset += 4; i++;
260*4882a593Smuzhiyun 		} while ((i <= p->end) && (p->end != -1));
261*4882a593Smuzhiyun 	}
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun 	spin_unlock_irqrestore(&mfp_spin_lock, flags);
264*4882a593Smuzhiyun }
265*4882a593Smuzhiyun 
mfp_config_lpm(void)266*4882a593Smuzhiyun void mfp_config_lpm(void)
267*4882a593Smuzhiyun {
268*4882a593Smuzhiyun 	struct mfp_pin *p = &mfp_table[0];
269*4882a593Smuzhiyun 	int pin;
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun 	for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++, p++)
272*4882a593Smuzhiyun 		__mfp_config_lpm(p);
273*4882a593Smuzhiyun }
274*4882a593Smuzhiyun 
mfp_config_run(void)275*4882a593Smuzhiyun void mfp_config_run(void)
276*4882a593Smuzhiyun {
277*4882a593Smuzhiyun 	struct mfp_pin *p = &mfp_table[0];
278*4882a593Smuzhiyun 	int pin;
279*4882a593Smuzhiyun 
280*4882a593Smuzhiyun 	for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++, p++)
281*4882a593Smuzhiyun 		__mfp_config_run(p);
282*4882a593Smuzhiyun }
283