1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * arch/arm/plat-orion/irq.c
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Marvell Orion SoC IRQ handling.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public
7*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any
8*4882a593Smuzhiyun * warranty of any kind, whether express or implied.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/irq.h>
14*4882a593Smuzhiyun #include <linux/irqdomain.h>
15*4882a593Smuzhiyun #include <linux/io.h>
16*4882a593Smuzhiyun #include <linux/of_address.h>
17*4882a593Smuzhiyun #include <linux/of_irq.h>
18*4882a593Smuzhiyun #include <asm/exception.h>
19*4882a593Smuzhiyun #include <plat/irq.h>
20*4882a593Smuzhiyun #include <plat/orion-gpio.h>
21*4882a593Smuzhiyun
orion_irq_init(unsigned int irq_start,void __iomem * maskaddr)22*4882a593Smuzhiyun void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun struct irq_chip_generic *gc;
25*4882a593Smuzhiyun struct irq_chip_type *ct;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /*
28*4882a593Smuzhiyun * Mask all interrupts initially.
29*4882a593Smuzhiyun */
30*4882a593Smuzhiyun writel(0, maskaddr);
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun gc = irq_alloc_generic_chip("orion_irq", 1, irq_start, maskaddr,
33*4882a593Smuzhiyun handle_level_irq);
34*4882a593Smuzhiyun ct = gc->chip_types;
35*4882a593Smuzhiyun ct->chip.irq_mask = irq_gc_mask_clr_bit;
36*4882a593Smuzhiyun ct->chip.irq_unmask = irq_gc_mask_set_bit;
37*4882a593Smuzhiyun irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_MASK_CACHE,
38*4882a593Smuzhiyun IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
39*4882a593Smuzhiyun }
40