1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * arch/arm/plat-orion/include/plat/pcie.h 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Marvell Orion SoC PCIe handling. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public 7*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any 8*4882a593Smuzhiyun * warranty of any kind, whether express or implied. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __PLAT_PCIE_H 12*4882a593Smuzhiyun #define __PLAT_PCIE_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun struct pci_bus; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun u32 orion_pcie_dev_id(void __iomem *base); 17*4882a593Smuzhiyun u32 orion_pcie_rev(void __iomem *base); 18*4882a593Smuzhiyun int orion_pcie_link_up(void __iomem *base); 19*4882a593Smuzhiyun int orion_pcie_x4_mode(void __iomem *base); 20*4882a593Smuzhiyun int orion_pcie_get_local_bus_nr(void __iomem *base); 21*4882a593Smuzhiyun void orion_pcie_set_local_bus_nr(void __iomem *base, int nr); 22*4882a593Smuzhiyun void orion_pcie_reset(void __iomem *base); 23*4882a593Smuzhiyun void orion_pcie_setup(void __iomem *base); 24*4882a593Smuzhiyun int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus, 25*4882a593Smuzhiyun u32 devfn, int where, int size, u32 *val); 26*4882a593Smuzhiyun int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus, 27*4882a593Smuzhiyun u32 devfn, int where, int size, u32 *val); 28*4882a593Smuzhiyun int orion_pcie_rd_conf_wa(void __iomem *wa_base, struct pci_bus *bus, 29*4882a593Smuzhiyun u32 devfn, int where, int size, u32 *val); 30*4882a593Smuzhiyun int orion_pcie_wr_conf(void __iomem *base, struct pci_bus *bus, 31*4882a593Smuzhiyun u32 devfn, int where, int size, u32 val); 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #endif 35