1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * arch/arm/plat-orion/common.c
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Marvell Orion SoC common setup code used by multiple mach-/common.c
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public
7*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any
8*4882a593Smuzhiyun * warranty of any kind, whether express or implied.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun #include <linux/dma-mapping.h>
15*4882a593Smuzhiyun #include <linux/serial_8250.h>
16*4882a593Smuzhiyun #include <linux/ata_platform.h>
17*4882a593Smuzhiyun #include <linux/clk.h>
18*4882a593Smuzhiyun #include <linux/clkdev.h>
19*4882a593Smuzhiyun #include <linux/mv643xx_eth.h>
20*4882a593Smuzhiyun #include <linux/mv643xx_i2c.h>
21*4882a593Smuzhiyun #include <linux/platform_data/dsa.h>
22*4882a593Smuzhiyun #include <linux/platform_data/dma-mv_xor.h>
23*4882a593Smuzhiyun #include <linux/platform_data/usb-ehci-orion.h>
24*4882a593Smuzhiyun #include <plat/common.h>
25*4882a593Smuzhiyun #include <linux/phy.h>
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /* Create a clkdev entry for a given device/clk */
orion_clkdev_add(const char * con_id,const char * dev_id,struct clk * clk)28*4882a593Smuzhiyun void __init orion_clkdev_add(const char *con_id, const char *dev_id,
29*4882a593Smuzhiyun struct clk *clk)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun clkdev_create(clk, con_id, "%s", dev_id);
32*4882a593Smuzhiyun }
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /* Create clkdev entries for all orion platforms except kirkwood.
35*4882a593Smuzhiyun Kirkwood has gated clocks for some of its peripherals, so creates
36*4882a593Smuzhiyun its own clkdev entries. For all the other orion devices, create
37*4882a593Smuzhiyun clkdev entries to the tclk. */
orion_clkdev_init(struct clk * tclk)38*4882a593Smuzhiyun void __init orion_clkdev_init(struct clk *tclk)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun orion_clkdev_add(NULL, "orion_spi.0", tclk);
41*4882a593Smuzhiyun orion_clkdev_add(NULL, "orion_spi.1", tclk);
42*4882a593Smuzhiyun orion_clkdev_add(NULL, MV643XX_ETH_NAME ".0", tclk);
43*4882a593Smuzhiyun orion_clkdev_add(NULL, MV643XX_ETH_NAME ".1", tclk);
44*4882a593Smuzhiyun orion_clkdev_add(NULL, MV643XX_ETH_NAME ".2", tclk);
45*4882a593Smuzhiyun orion_clkdev_add(NULL, MV643XX_ETH_NAME ".3", tclk);
46*4882a593Smuzhiyun orion_clkdev_add(NULL, "orion_wdt", tclk);
47*4882a593Smuzhiyun orion_clkdev_add(NULL, MV64XXX_I2C_CTLR_NAME ".0", tclk);
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /* Fill in the resources structure and link it into the platform
51*4882a593Smuzhiyun device structure. There is always a memory region, and nearly
52*4882a593Smuzhiyun always an interrupt.*/
fill_resources(struct platform_device * device,struct resource * resources,resource_size_t mapbase,resource_size_t size)53*4882a593Smuzhiyun static void fill_resources(struct platform_device *device,
54*4882a593Smuzhiyun struct resource *resources,
55*4882a593Smuzhiyun resource_size_t mapbase,
56*4882a593Smuzhiyun resource_size_t size)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun device->resource = resources;
59*4882a593Smuzhiyun device->num_resources = 1;
60*4882a593Smuzhiyun resources[0].flags = IORESOURCE_MEM;
61*4882a593Smuzhiyun resources[0].start = mapbase;
62*4882a593Smuzhiyun resources[0].end = mapbase + size;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
fill_resources_irq(struct platform_device * device,struct resource * resources,resource_size_t mapbase,resource_size_t size,unsigned int irq)65*4882a593Smuzhiyun static void fill_resources_irq(struct platform_device *device,
66*4882a593Smuzhiyun struct resource *resources,
67*4882a593Smuzhiyun resource_size_t mapbase,
68*4882a593Smuzhiyun resource_size_t size,
69*4882a593Smuzhiyun unsigned int irq)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun fill_resources(device, resources, mapbase, size);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun device->num_resources++;
74*4882a593Smuzhiyun resources[1].flags = IORESOURCE_IRQ;
75*4882a593Smuzhiyun resources[1].start = irq;
76*4882a593Smuzhiyun resources[1].end = irq;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun /*****************************************************************************
80*4882a593Smuzhiyun * UART
81*4882a593Smuzhiyun ****************************************************************************/
uart_get_clk_rate(struct clk * clk)82*4882a593Smuzhiyun static unsigned long __init uart_get_clk_rate(struct clk *clk)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun clk_prepare_enable(clk);
85*4882a593Smuzhiyun return clk_get_rate(clk);
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
uart_complete(struct platform_device * orion_uart,struct plat_serial8250_port * data,struct resource * resources,void __iomem * membase,resource_size_t mapbase,unsigned int irq,struct clk * clk)88*4882a593Smuzhiyun static void __init uart_complete(
89*4882a593Smuzhiyun struct platform_device *orion_uart,
90*4882a593Smuzhiyun struct plat_serial8250_port *data,
91*4882a593Smuzhiyun struct resource *resources,
92*4882a593Smuzhiyun void __iomem *membase,
93*4882a593Smuzhiyun resource_size_t mapbase,
94*4882a593Smuzhiyun unsigned int irq,
95*4882a593Smuzhiyun struct clk *clk)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun data->mapbase = mapbase;
98*4882a593Smuzhiyun data->membase = membase;
99*4882a593Smuzhiyun data->irq = irq;
100*4882a593Smuzhiyun data->uartclk = uart_get_clk_rate(clk);
101*4882a593Smuzhiyun orion_uart->dev.platform_data = data;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun fill_resources_irq(orion_uart, resources, mapbase, 0xff, irq);
104*4882a593Smuzhiyun platform_device_register(orion_uart);
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun /*****************************************************************************
108*4882a593Smuzhiyun * UART0
109*4882a593Smuzhiyun ****************************************************************************/
110*4882a593Smuzhiyun static struct plat_serial8250_port orion_uart0_data[] = {
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
113*4882a593Smuzhiyun .iotype = UPIO_MEM,
114*4882a593Smuzhiyun .regshift = 2,
115*4882a593Smuzhiyun }, {
116*4882a593Smuzhiyun },
117*4882a593Smuzhiyun };
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun static struct resource orion_uart0_resources[2];
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun static struct platform_device orion_uart0 = {
122*4882a593Smuzhiyun .name = "serial8250",
123*4882a593Smuzhiyun .id = PLAT8250_DEV_PLATFORM,
124*4882a593Smuzhiyun };
125*4882a593Smuzhiyun
orion_uart0_init(void __iomem * membase,resource_size_t mapbase,unsigned int irq,struct clk * clk)126*4882a593Smuzhiyun void __init orion_uart0_init(void __iomem *membase,
127*4882a593Smuzhiyun resource_size_t mapbase,
128*4882a593Smuzhiyun unsigned int irq,
129*4882a593Smuzhiyun struct clk *clk)
130*4882a593Smuzhiyun {
131*4882a593Smuzhiyun uart_complete(&orion_uart0, orion_uart0_data, orion_uart0_resources,
132*4882a593Smuzhiyun membase, mapbase, irq, clk);
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun /*****************************************************************************
136*4882a593Smuzhiyun * UART1
137*4882a593Smuzhiyun ****************************************************************************/
138*4882a593Smuzhiyun static struct plat_serial8250_port orion_uart1_data[] = {
139*4882a593Smuzhiyun {
140*4882a593Smuzhiyun .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
141*4882a593Smuzhiyun .iotype = UPIO_MEM,
142*4882a593Smuzhiyun .regshift = 2,
143*4882a593Smuzhiyun }, {
144*4882a593Smuzhiyun },
145*4882a593Smuzhiyun };
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun static struct resource orion_uart1_resources[2];
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun static struct platform_device orion_uart1 = {
150*4882a593Smuzhiyun .name = "serial8250",
151*4882a593Smuzhiyun .id = PLAT8250_DEV_PLATFORM1,
152*4882a593Smuzhiyun };
153*4882a593Smuzhiyun
orion_uart1_init(void __iomem * membase,resource_size_t mapbase,unsigned int irq,struct clk * clk)154*4882a593Smuzhiyun void __init orion_uart1_init(void __iomem *membase,
155*4882a593Smuzhiyun resource_size_t mapbase,
156*4882a593Smuzhiyun unsigned int irq,
157*4882a593Smuzhiyun struct clk *clk)
158*4882a593Smuzhiyun {
159*4882a593Smuzhiyun uart_complete(&orion_uart1, orion_uart1_data, orion_uart1_resources,
160*4882a593Smuzhiyun membase, mapbase, irq, clk);
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun /*****************************************************************************
164*4882a593Smuzhiyun * UART2
165*4882a593Smuzhiyun ****************************************************************************/
166*4882a593Smuzhiyun static struct plat_serial8250_port orion_uart2_data[] = {
167*4882a593Smuzhiyun {
168*4882a593Smuzhiyun .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
169*4882a593Smuzhiyun .iotype = UPIO_MEM,
170*4882a593Smuzhiyun .regshift = 2,
171*4882a593Smuzhiyun }, {
172*4882a593Smuzhiyun },
173*4882a593Smuzhiyun };
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun static struct resource orion_uart2_resources[2];
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun static struct platform_device orion_uart2 = {
178*4882a593Smuzhiyun .name = "serial8250",
179*4882a593Smuzhiyun .id = PLAT8250_DEV_PLATFORM2,
180*4882a593Smuzhiyun };
181*4882a593Smuzhiyun
orion_uart2_init(void __iomem * membase,resource_size_t mapbase,unsigned int irq,struct clk * clk)182*4882a593Smuzhiyun void __init orion_uart2_init(void __iomem *membase,
183*4882a593Smuzhiyun resource_size_t mapbase,
184*4882a593Smuzhiyun unsigned int irq,
185*4882a593Smuzhiyun struct clk *clk)
186*4882a593Smuzhiyun {
187*4882a593Smuzhiyun uart_complete(&orion_uart2, orion_uart2_data, orion_uart2_resources,
188*4882a593Smuzhiyun membase, mapbase, irq, clk);
189*4882a593Smuzhiyun }
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun /*****************************************************************************
192*4882a593Smuzhiyun * UART3
193*4882a593Smuzhiyun ****************************************************************************/
194*4882a593Smuzhiyun static struct plat_serial8250_port orion_uart3_data[] = {
195*4882a593Smuzhiyun {
196*4882a593Smuzhiyun .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
197*4882a593Smuzhiyun .iotype = UPIO_MEM,
198*4882a593Smuzhiyun .regshift = 2,
199*4882a593Smuzhiyun }, {
200*4882a593Smuzhiyun },
201*4882a593Smuzhiyun };
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun static struct resource orion_uart3_resources[2];
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun static struct platform_device orion_uart3 = {
206*4882a593Smuzhiyun .name = "serial8250",
207*4882a593Smuzhiyun .id = 3,
208*4882a593Smuzhiyun };
209*4882a593Smuzhiyun
orion_uart3_init(void __iomem * membase,resource_size_t mapbase,unsigned int irq,struct clk * clk)210*4882a593Smuzhiyun void __init orion_uart3_init(void __iomem *membase,
211*4882a593Smuzhiyun resource_size_t mapbase,
212*4882a593Smuzhiyun unsigned int irq,
213*4882a593Smuzhiyun struct clk *clk)
214*4882a593Smuzhiyun {
215*4882a593Smuzhiyun uart_complete(&orion_uart3, orion_uart3_data, orion_uart3_resources,
216*4882a593Smuzhiyun membase, mapbase, irq, clk);
217*4882a593Smuzhiyun }
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun /*****************************************************************************
220*4882a593Smuzhiyun * SoC RTC
221*4882a593Smuzhiyun ****************************************************************************/
222*4882a593Smuzhiyun static struct resource orion_rtc_resource[2];
223*4882a593Smuzhiyun
orion_rtc_init(unsigned long mapbase,unsigned long irq)224*4882a593Smuzhiyun void __init orion_rtc_init(unsigned long mapbase,
225*4882a593Smuzhiyun unsigned long irq)
226*4882a593Smuzhiyun {
227*4882a593Smuzhiyun orion_rtc_resource[0].start = mapbase;
228*4882a593Smuzhiyun orion_rtc_resource[0].end = mapbase + SZ_32 - 1;
229*4882a593Smuzhiyun orion_rtc_resource[0].flags = IORESOURCE_MEM;
230*4882a593Smuzhiyun orion_rtc_resource[1].start = irq;
231*4882a593Smuzhiyun orion_rtc_resource[1].end = irq;
232*4882a593Smuzhiyun orion_rtc_resource[1].flags = IORESOURCE_IRQ;
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun platform_device_register_simple("rtc-mv", -1, orion_rtc_resource, 2);
235*4882a593Smuzhiyun }
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun /*****************************************************************************
238*4882a593Smuzhiyun * GE
239*4882a593Smuzhiyun ****************************************************************************/
ge_complete(struct mv643xx_eth_shared_platform_data * orion_ge_shared_data,struct resource * orion_ge_resource,unsigned long irq,struct platform_device * orion_ge_shared,struct platform_device * orion_ge_mvmdio,struct mv643xx_eth_platform_data * eth_data,struct platform_device * orion_ge)240*4882a593Smuzhiyun static __init void ge_complete(
241*4882a593Smuzhiyun struct mv643xx_eth_shared_platform_data *orion_ge_shared_data,
242*4882a593Smuzhiyun struct resource *orion_ge_resource, unsigned long irq,
243*4882a593Smuzhiyun struct platform_device *orion_ge_shared,
244*4882a593Smuzhiyun struct platform_device *orion_ge_mvmdio,
245*4882a593Smuzhiyun struct mv643xx_eth_platform_data *eth_data,
246*4882a593Smuzhiyun struct platform_device *orion_ge)
247*4882a593Smuzhiyun {
248*4882a593Smuzhiyun orion_ge_resource->start = irq;
249*4882a593Smuzhiyun orion_ge_resource->end = irq;
250*4882a593Smuzhiyun eth_data->shared = orion_ge_shared;
251*4882a593Smuzhiyun orion_ge->dev.platform_data = eth_data;
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun platform_device_register(orion_ge_shared);
254*4882a593Smuzhiyun if (orion_ge_mvmdio)
255*4882a593Smuzhiyun platform_device_register(orion_ge_mvmdio);
256*4882a593Smuzhiyun platform_device_register(orion_ge);
257*4882a593Smuzhiyun }
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun /*****************************************************************************
260*4882a593Smuzhiyun * GE00
261*4882a593Smuzhiyun ****************************************************************************/
262*4882a593Smuzhiyun static struct mv643xx_eth_shared_platform_data orion_ge00_shared_data;
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun static struct resource orion_ge00_shared_resources[] = {
265*4882a593Smuzhiyun {
266*4882a593Smuzhiyun .name = "ge00 base",
267*4882a593Smuzhiyun },
268*4882a593Smuzhiyun };
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun static struct platform_device orion_ge00_shared = {
271*4882a593Smuzhiyun .name = MV643XX_ETH_SHARED_NAME,
272*4882a593Smuzhiyun .id = 0,
273*4882a593Smuzhiyun .dev = {
274*4882a593Smuzhiyun .platform_data = &orion_ge00_shared_data,
275*4882a593Smuzhiyun },
276*4882a593Smuzhiyun };
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun static struct resource orion_ge_mvmdio_resources[] = {
279*4882a593Smuzhiyun {
280*4882a593Smuzhiyun .name = "ge00 mvmdio base",
281*4882a593Smuzhiyun }, {
282*4882a593Smuzhiyun .name = "ge00 mvmdio err irq",
283*4882a593Smuzhiyun },
284*4882a593Smuzhiyun };
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun static struct platform_device orion_ge_mvmdio = {
287*4882a593Smuzhiyun .name = "orion-mdio",
288*4882a593Smuzhiyun .id = -1,
289*4882a593Smuzhiyun };
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun static struct resource orion_ge00_resources[] = {
292*4882a593Smuzhiyun {
293*4882a593Smuzhiyun .name = "ge00 irq",
294*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
295*4882a593Smuzhiyun },
296*4882a593Smuzhiyun };
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun static struct platform_device orion_ge00 = {
299*4882a593Smuzhiyun .name = MV643XX_ETH_NAME,
300*4882a593Smuzhiyun .id = 0,
301*4882a593Smuzhiyun .num_resources = 1,
302*4882a593Smuzhiyun .resource = orion_ge00_resources,
303*4882a593Smuzhiyun .dev = {
304*4882a593Smuzhiyun .coherent_dma_mask = DMA_BIT_MASK(32),
305*4882a593Smuzhiyun },
306*4882a593Smuzhiyun };
307*4882a593Smuzhiyun
orion_ge00_init(struct mv643xx_eth_platform_data * eth_data,unsigned long mapbase,unsigned long irq,unsigned long irq_err,unsigned int tx_csum_limit)308*4882a593Smuzhiyun void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
309*4882a593Smuzhiyun unsigned long mapbase,
310*4882a593Smuzhiyun unsigned long irq,
311*4882a593Smuzhiyun unsigned long irq_err,
312*4882a593Smuzhiyun unsigned int tx_csum_limit)
313*4882a593Smuzhiyun {
314*4882a593Smuzhiyun fill_resources(&orion_ge00_shared, orion_ge00_shared_resources,
315*4882a593Smuzhiyun mapbase + 0x2000, SZ_16K - 1);
316*4882a593Smuzhiyun fill_resources_irq(&orion_ge_mvmdio, orion_ge_mvmdio_resources,
317*4882a593Smuzhiyun mapbase + 0x2004, 0x84 - 1, irq_err);
318*4882a593Smuzhiyun orion_ge00_shared_data.tx_csum_limit = tx_csum_limit;
319*4882a593Smuzhiyun ge_complete(&orion_ge00_shared_data,
320*4882a593Smuzhiyun orion_ge00_resources, irq, &orion_ge00_shared,
321*4882a593Smuzhiyun &orion_ge_mvmdio,
322*4882a593Smuzhiyun eth_data, &orion_ge00);
323*4882a593Smuzhiyun }
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun /*****************************************************************************
326*4882a593Smuzhiyun * GE01
327*4882a593Smuzhiyun ****************************************************************************/
328*4882a593Smuzhiyun static struct mv643xx_eth_shared_platform_data orion_ge01_shared_data;
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun static struct resource orion_ge01_shared_resources[] = {
331*4882a593Smuzhiyun {
332*4882a593Smuzhiyun .name = "ge01 base",
333*4882a593Smuzhiyun }
334*4882a593Smuzhiyun };
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun static struct platform_device orion_ge01_shared = {
337*4882a593Smuzhiyun .name = MV643XX_ETH_SHARED_NAME,
338*4882a593Smuzhiyun .id = 1,
339*4882a593Smuzhiyun .dev = {
340*4882a593Smuzhiyun .platform_data = &orion_ge01_shared_data,
341*4882a593Smuzhiyun },
342*4882a593Smuzhiyun };
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun static struct resource orion_ge01_resources[] = {
345*4882a593Smuzhiyun {
346*4882a593Smuzhiyun .name = "ge01 irq",
347*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
348*4882a593Smuzhiyun },
349*4882a593Smuzhiyun };
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun static struct platform_device orion_ge01 = {
352*4882a593Smuzhiyun .name = MV643XX_ETH_NAME,
353*4882a593Smuzhiyun .id = 1,
354*4882a593Smuzhiyun .num_resources = 1,
355*4882a593Smuzhiyun .resource = orion_ge01_resources,
356*4882a593Smuzhiyun .dev = {
357*4882a593Smuzhiyun .coherent_dma_mask = DMA_BIT_MASK(32),
358*4882a593Smuzhiyun },
359*4882a593Smuzhiyun };
360*4882a593Smuzhiyun
orion_ge01_init(struct mv643xx_eth_platform_data * eth_data,unsigned long mapbase,unsigned long irq,unsigned int tx_csum_limit)361*4882a593Smuzhiyun void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data,
362*4882a593Smuzhiyun unsigned long mapbase,
363*4882a593Smuzhiyun unsigned long irq,
364*4882a593Smuzhiyun unsigned int tx_csum_limit)
365*4882a593Smuzhiyun {
366*4882a593Smuzhiyun fill_resources(&orion_ge01_shared, orion_ge01_shared_resources,
367*4882a593Smuzhiyun mapbase + 0x2000, SZ_16K - 1);
368*4882a593Smuzhiyun orion_ge01_shared_data.tx_csum_limit = tx_csum_limit;
369*4882a593Smuzhiyun ge_complete(&orion_ge01_shared_data,
370*4882a593Smuzhiyun orion_ge01_resources, irq, &orion_ge01_shared,
371*4882a593Smuzhiyun NULL,
372*4882a593Smuzhiyun eth_data, &orion_ge01);
373*4882a593Smuzhiyun }
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun /*****************************************************************************
376*4882a593Smuzhiyun * GE10
377*4882a593Smuzhiyun ****************************************************************************/
378*4882a593Smuzhiyun static struct mv643xx_eth_shared_platform_data orion_ge10_shared_data;
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun static struct resource orion_ge10_shared_resources[] = {
381*4882a593Smuzhiyun {
382*4882a593Smuzhiyun .name = "ge10 base",
383*4882a593Smuzhiyun }
384*4882a593Smuzhiyun };
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun static struct platform_device orion_ge10_shared = {
387*4882a593Smuzhiyun .name = MV643XX_ETH_SHARED_NAME,
388*4882a593Smuzhiyun .id = 2,
389*4882a593Smuzhiyun .dev = {
390*4882a593Smuzhiyun .platform_data = &orion_ge10_shared_data,
391*4882a593Smuzhiyun },
392*4882a593Smuzhiyun };
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun static struct resource orion_ge10_resources[] = {
395*4882a593Smuzhiyun {
396*4882a593Smuzhiyun .name = "ge10 irq",
397*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
398*4882a593Smuzhiyun },
399*4882a593Smuzhiyun };
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun static struct platform_device orion_ge10 = {
402*4882a593Smuzhiyun .name = MV643XX_ETH_NAME,
403*4882a593Smuzhiyun .id = 2,
404*4882a593Smuzhiyun .num_resources = 1,
405*4882a593Smuzhiyun .resource = orion_ge10_resources,
406*4882a593Smuzhiyun .dev = {
407*4882a593Smuzhiyun .coherent_dma_mask = DMA_BIT_MASK(32),
408*4882a593Smuzhiyun },
409*4882a593Smuzhiyun };
410*4882a593Smuzhiyun
orion_ge10_init(struct mv643xx_eth_platform_data * eth_data,unsigned long mapbase,unsigned long irq)411*4882a593Smuzhiyun void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data,
412*4882a593Smuzhiyun unsigned long mapbase,
413*4882a593Smuzhiyun unsigned long irq)
414*4882a593Smuzhiyun {
415*4882a593Smuzhiyun fill_resources(&orion_ge10_shared, orion_ge10_shared_resources,
416*4882a593Smuzhiyun mapbase + 0x2000, SZ_16K - 1);
417*4882a593Smuzhiyun ge_complete(&orion_ge10_shared_data,
418*4882a593Smuzhiyun orion_ge10_resources, irq, &orion_ge10_shared,
419*4882a593Smuzhiyun NULL,
420*4882a593Smuzhiyun eth_data, &orion_ge10);
421*4882a593Smuzhiyun }
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun /*****************************************************************************
424*4882a593Smuzhiyun * GE11
425*4882a593Smuzhiyun ****************************************************************************/
426*4882a593Smuzhiyun static struct mv643xx_eth_shared_platform_data orion_ge11_shared_data;
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun static struct resource orion_ge11_shared_resources[] = {
429*4882a593Smuzhiyun {
430*4882a593Smuzhiyun .name = "ge11 base",
431*4882a593Smuzhiyun },
432*4882a593Smuzhiyun };
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun static struct platform_device orion_ge11_shared = {
435*4882a593Smuzhiyun .name = MV643XX_ETH_SHARED_NAME,
436*4882a593Smuzhiyun .id = 3,
437*4882a593Smuzhiyun .dev = {
438*4882a593Smuzhiyun .platform_data = &orion_ge11_shared_data,
439*4882a593Smuzhiyun },
440*4882a593Smuzhiyun };
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun static struct resource orion_ge11_resources[] = {
443*4882a593Smuzhiyun {
444*4882a593Smuzhiyun .name = "ge11 irq",
445*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
446*4882a593Smuzhiyun },
447*4882a593Smuzhiyun };
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun static struct platform_device orion_ge11 = {
450*4882a593Smuzhiyun .name = MV643XX_ETH_NAME,
451*4882a593Smuzhiyun .id = 3,
452*4882a593Smuzhiyun .num_resources = 1,
453*4882a593Smuzhiyun .resource = orion_ge11_resources,
454*4882a593Smuzhiyun .dev = {
455*4882a593Smuzhiyun .coherent_dma_mask = DMA_BIT_MASK(32),
456*4882a593Smuzhiyun },
457*4882a593Smuzhiyun };
458*4882a593Smuzhiyun
orion_ge11_init(struct mv643xx_eth_platform_data * eth_data,unsigned long mapbase,unsigned long irq)459*4882a593Smuzhiyun void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data,
460*4882a593Smuzhiyun unsigned long mapbase,
461*4882a593Smuzhiyun unsigned long irq)
462*4882a593Smuzhiyun {
463*4882a593Smuzhiyun fill_resources(&orion_ge11_shared, orion_ge11_shared_resources,
464*4882a593Smuzhiyun mapbase + 0x2000, SZ_16K - 1);
465*4882a593Smuzhiyun ge_complete(&orion_ge11_shared_data,
466*4882a593Smuzhiyun orion_ge11_resources, irq, &orion_ge11_shared,
467*4882a593Smuzhiyun NULL,
468*4882a593Smuzhiyun eth_data, &orion_ge11);
469*4882a593Smuzhiyun }
470*4882a593Smuzhiyun
471*4882a593Smuzhiyun #ifdef CONFIG_ARCH_ORION5X
472*4882a593Smuzhiyun /*****************************************************************************
473*4882a593Smuzhiyun * Ethernet switch
474*4882a593Smuzhiyun ****************************************************************************/
475*4882a593Smuzhiyun static __initdata struct mdio_board_info orion_ge00_switch_board_info = {
476*4882a593Smuzhiyun .bus_id = "orion-mii",
477*4882a593Smuzhiyun .modalias = "mv88e6085",
478*4882a593Smuzhiyun };
479*4882a593Smuzhiyun
orion_ge00_switch_init(struct dsa_chip_data * d)480*4882a593Smuzhiyun void __init orion_ge00_switch_init(struct dsa_chip_data *d)
481*4882a593Smuzhiyun {
482*4882a593Smuzhiyun unsigned int i;
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun if (!IS_BUILTIN(CONFIG_PHYLIB))
485*4882a593Smuzhiyun return;
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(d->port_names); i++) {
488*4882a593Smuzhiyun if (!strcmp(d->port_names[i], "cpu")) {
489*4882a593Smuzhiyun d->netdev[i] = &orion_ge00.dev;
490*4882a593Smuzhiyun break;
491*4882a593Smuzhiyun }
492*4882a593Smuzhiyun }
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun orion_ge00_switch_board_info.mdio_addr = d->sw_addr;
495*4882a593Smuzhiyun orion_ge00_switch_board_info.platform_data = d;
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun mdiobus_register_board_info(&orion_ge00_switch_board_info, 1);
498*4882a593Smuzhiyun }
499*4882a593Smuzhiyun #endif
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun /*****************************************************************************
502*4882a593Smuzhiyun * I2C
503*4882a593Smuzhiyun ****************************************************************************/
504*4882a593Smuzhiyun static struct mv64xxx_i2c_pdata orion_i2c_pdata = {
505*4882a593Smuzhiyun .freq_n = 3,
506*4882a593Smuzhiyun .timeout = 1000, /* Default timeout of 1 second */
507*4882a593Smuzhiyun };
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun static struct resource orion_i2c_resources[2];
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun static struct platform_device orion_i2c = {
512*4882a593Smuzhiyun .name = MV64XXX_I2C_CTLR_NAME,
513*4882a593Smuzhiyun .id = 0,
514*4882a593Smuzhiyun .dev = {
515*4882a593Smuzhiyun .platform_data = &orion_i2c_pdata,
516*4882a593Smuzhiyun },
517*4882a593Smuzhiyun };
518*4882a593Smuzhiyun
519*4882a593Smuzhiyun static struct mv64xxx_i2c_pdata orion_i2c_1_pdata = {
520*4882a593Smuzhiyun .freq_n = 3,
521*4882a593Smuzhiyun .timeout = 1000, /* Default timeout of 1 second */
522*4882a593Smuzhiyun };
523*4882a593Smuzhiyun
524*4882a593Smuzhiyun static struct resource orion_i2c_1_resources[2];
525*4882a593Smuzhiyun
526*4882a593Smuzhiyun static struct platform_device orion_i2c_1 = {
527*4882a593Smuzhiyun .name = MV64XXX_I2C_CTLR_NAME,
528*4882a593Smuzhiyun .id = 1,
529*4882a593Smuzhiyun .dev = {
530*4882a593Smuzhiyun .platform_data = &orion_i2c_1_pdata,
531*4882a593Smuzhiyun },
532*4882a593Smuzhiyun };
533*4882a593Smuzhiyun
orion_i2c_init(unsigned long mapbase,unsigned long irq,unsigned long freq_m)534*4882a593Smuzhiyun void __init orion_i2c_init(unsigned long mapbase,
535*4882a593Smuzhiyun unsigned long irq,
536*4882a593Smuzhiyun unsigned long freq_m)
537*4882a593Smuzhiyun {
538*4882a593Smuzhiyun orion_i2c_pdata.freq_m = freq_m;
539*4882a593Smuzhiyun fill_resources_irq(&orion_i2c, orion_i2c_resources, mapbase,
540*4882a593Smuzhiyun SZ_32 - 1, irq);
541*4882a593Smuzhiyun platform_device_register(&orion_i2c);
542*4882a593Smuzhiyun }
543*4882a593Smuzhiyun
orion_i2c_1_init(unsigned long mapbase,unsigned long irq,unsigned long freq_m)544*4882a593Smuzhiyun void __init orion_i2c_1_init(unsigned long mapbase,
545*4882a593Smuzhiyun unsigned long irq,
546*4882a593Smuzhiyun unsigned long freq_m)
547*4882a593Smuzhiyun {
548*4882a593Smuzhiyun orion_i2c_1_pdata.freq_m = freq_m;
549*4882a593Smuzhiyun fill_resources_irq(&orion_i2c_1, orion_i2c_1_resources, mapbase,
550*4882a593Smuzhiyun SZ_32 - 1, irq);
551*4882a593Smuzhiyun platform_device_register(&orion_i2c_1);
552*4882a593Smuzhiyun }
553*4882a593Smuzhiyun
554*4882a593Smuzhiyun /*****************************************************************************
555*4882a593Smuzhiyun * SPI
556*4882a593Smuzhiyun ****************************************************************************/
557*4882a593Smuzhiyun static struct resource orion_spi_resources;
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun static struct platform_device orion_spi = {
560*4882a593Smuzhiyun .name = "orion_spi",
561*4882a593Smuzhiyun .id = 0,
562*4882a593Smuzhiyun };
563*4882a593Smuzhiyun
564*4882a593Smuzhiyun static struct resource orion_spi_1_resources;
565*4882a593Smuzhiyun
566*4882a593Smuzhiyun static struct platform_device orion_spi_1 = {
567*4882a593Smuzhiyun .name = "orion_spi",
568*4882a593Smuzhiyun .id = 1,
569*4882a593Smuzhiyun };
570*4882a593Smuzhiyun
571*4882a593Smuzhiyun /* Note: The SPI silicon core does have interrupts. However the
572*4882a593Smuzhiyun * current Linux software driver does not use interrupts. */
573*4882a593Smuzhiyun
orion_spi_init(unsigned long mapbase)574*4882a593Smuzhiyun void __init orion_spi_init(unsigned long mapbase)
575*4882a593Smuzhiyun {
576*4882a593Smuzhiyun fill_resources(&orion_spi, &orion_spi_resources,
577*4882a593Smuzhiyun mapbase, SZ_512 - 1);
578*4882a593Smuzhiyun platform_device_register(&orion_spi);
579*4882a593Smuzhiyun }
580*4882a593Smuzhiyun
orion_spi_1_init(unsigned long mapbase)581*4882a593Smuzhiyun void __init orion_spi_1_init(unsigned long mapbase)
582*4882a593Smuzhiyun {
583*4882a593Smuzhiyun fill_resources(&orion_spi_1, &orion_spi_1_resources,
584*4882a593Smuzhiyun mapbase, SZ_512 - 1);
585*4882a593Smuzhiyun platform_device_register(&orion_spi_1);
586*4882a593Smuzhiyun }
587*4882a593Smuzhiyun
588*4882a593Smuzhiyun /*****************************************************************************
589*4882a593Smuzhiyun * XOR
590*4882a593Smuzhiyun ****************************************************************************/
591*4882a593Smuzhiyun static u64 orion_xor_dmamask = DMA_BIT_MASK(32);
592*4882a593Smuzhiyun
593*4882a593Smuzhiyun /*****************************************************************************
594*4882a593Smuzhiyun * XOR0
595*4882a593Smuzhiyun ****************************************************************************/
596*4882a593Smuzhiyun static struct resource orion_xor0_shared_resources[] = {
597*4882a593Smuzhiyun {
598*4882a593Smuzhiyun .name = "xor 0 low",
599*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
600*4882a593Smuzhiyun }, {
601*4882a593Smuzhiyun .name = "xor 0 high",
602*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
603*4882a593Smuzhiyun }, {
604*4882a593Smuzhiyun .name = "irq channel 0",
605*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
606*4882a593Smuzhiyun }, {
607*4882a593Smuzhiyun .name = "irq channel 1",
608*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
609*4882a593Smuzhiyun },
610*4882a593Smuzhiyun };
611*4882a593Smuzhiyun
612*4882a593Smuzhiyun static struct mv_xor_channel_data orion_xor0_channels_data[2];
613*4882a593Smuzhiyun
614*4882a593Smuzhiyun static struct mv_xor_platform_data orion_xor0_pdata = {
615*4882a593Smuzhiyun .channels = orion_xor0_channels_data,
616*4882a593Smuzhiyun };
617*4882a593Smuzhiyun
618*4882a593Smuzhiyun static struct platform_device orion_xor0_shared = {
619*4882a593Smuzhiyun .name = MV_XOR_NAME,
620*4882a593Smuzhiyun .id = 0,
621*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(orion_xor0_shared_resources),
622*4882a593Smuzhiyun .resource = orion_xor0_shared_resources,
623*4882a593Smuzhiyun .dev = {
624*4882a593Smuzhiyun .dma_mask = &orion_xor_dmamask,
625*4882a593Smuzhiyun .coherent_dma_mask = DMA_BIT_MASK(32),
626*4882a593Smuzhiyun .platform_data = &orion_xor0_pdata,
627*4882a593Smuzhiyun },
628*4882a593Smuzhiyun };
629*4882a593Smuzhiyun
orion_xor0_init(unsigned long mapbase_low,unsigned long mapbase_high,unsigned long irq_0,unsigned long irq_1)630*4882a593Smuzhiyun void __init orion_xor0_init(unsigned long mapbase_low,
631*4882a593Smuzhiyun unsigned long mapbase_high,
632*4882a593Smuzhiyun unsigned long irq_0,
633*4882a593Smuzhiyun unsigned long irq_1)
634*4882a593Smuzhiyun {
635*4882a593Smuzhiyun orion_xor0_shared_resources[0].start = mapbase_low;
636*4882a593Smuzhiyun orion_xor0_shared_resources[0].end = mapbase_low + 0xff;
637*4882a593Smuzhiyun orion_xor0_shared_resources[1].start = mapbase_high;
638*4882a593Smuzhiyun orion_xor0_shared_resources[1].end = mapbase_high + 0xff;
639*4882a593Smuzhiyun
640*4882a593Smuzhiyun orion_xor0_shared_resources[2].start = irq_0;
641*4882a593Smuzhiyun orion_xor0_shared_resources[2].end = irq_0;
642*4882a593Smuzhiyun orion_xor0_shared_resources[3].start = irq_1;
643*4882a593Smuzhiyun orion_xor0_shared_resources[3].end = irq_1;
644*4882a593Smuzhiyun
645*4882a593Smuzhiyun dma_cap_set(DMA_MEMCPY, orion_xor0_channels_data[0].cap_mask);
646*4882a593Smuzhiyun dma_cap_set(DMA_XOR, orion_xor0_channels_data[0].cap_mask);
647*4882a593Smuzhiyun
648*4882a593Smuzhiyun dma_cap_set(DMA_MEMCPY, orion_xor0_channels_data[1].cap_mask);
649*4882a593Smuzhiyun dma_cap_set(DMA_XOR, orion_xor0_channels_data[1].cap_mask);
650*4882a593Smuzhiyun
651*4882a593Smuzhiyun platform_device_register(&orion_xor0_shared);
652*4882a593Smuzhiyun }
653*4882a593Smuzhiyun
654*4882a593Smuzhiyun /*****************************************************************************
655*4882a593Smuzhiyun * XOR1
656*4882a593Smuzhiyun ****************************************************************************/
657*4882a593Smuzhiyun static struct resource orion_xor1_shared_resources[] = {
658*4882a593Smuzhiyun {
659*4882a593Smuzhiyun .name = "xor 1 low",
660*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
661*4882a593Smuzhiyun }, {
662*4882a593Smuzhiyun .name = "xor 1 high",
663*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
664*4882a593Smuzhiyun }, {
665*4882a593Smuzhiyun .name = "irq channel 0",
666*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
667*4882a593Smuzhiyun }, {
668*4882a593Smuzhiyun .name = "irq channel 1",
669*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
670*4882a593Smuzhiyun },
671*4882a593Smuzhiyun };
672*4882a593Smuzhiyun
673*4882a593Smuzhiyun static struct mv_xor_channel_data orion_xor1_channels_data[2];
674*4882a593Smuzhiyun
675*4882a593Smuzhiyun static struct mv_xor_platform_data orion_xor1_pdata = {
676*4882a593Smuzhiyun .channels = orion_xor1_channels_data,
677*4882a593Smuzhiyun };
678*4882a593Smuzhiyun
679*4882a593Smuzhiyun static struct platform_device orion_xor1_shared = {
680*4882a593Smuzhiyun .name = MV_XOR_NAME,
681*4882a593Smuzhiyun .id = 1,
682*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(orion_xor1_shared_resources),
683*4882a593Smuzhiyun .resource = orion_xor1_shared_resources,
684*4882a593Smuzhiyun .dev = {
685*4882a593Smuzhiyun .dma_mask = &orion_xor_dmamask,
686*4882a593Smuzhiyun .coherent_dma_mask = DMA_BIT_MASK(32),
687*4882a593Smuzhiyun .platform_data = &orion_xor1_pdata,
688*4882a593Smuzhiyun },
689*4882a593Smuzhiyun };
690*4882a593Smuzhiyun
orion_xor1_init(unsigned long mapbase_low,unsigned long mapbase_high,unsigned long irq_0,unsigned long irq_1)691*4882a593Smuzhiyun void __init orion_xor1_init(unsigned long mapbase_low,
692*4882a593Smuzhiyun unsigned long mapbase_high,
693*4882a593Smuzhiyun unsigned long irq_0,
694*4882a593Smuzhiyun unsigned long irq_1)
695*4882a593Smuzhiyun {
696*4882a593Smuzhiyun orion_xor1_shared_resources[0].start = mapbase_low;
697*4882a593Smuzhiyun orion_xor1_shared_resources[0].end = mapbase_low + 0xff;
698*4882a593Smuzhiyun orion_xor1_shared_resources[1].start = mapbase_high;
699*4882a593Smuzhiyun orion_xor1_shared_resources[1].end = mapbase_high + 0xff;
700*4882a593Smuzhiyun
701*4882a593Smuzhiyun orion_xor1_shared_resources[2].start = irq_0;
702*4882a593Smuzhiyun orion_xor1_shared_resources[2].end = irq_0;
703*4882a593Smuzhiyun orion_xor1_shared_resources[3].start = irq_1;
704*4882a593Smuzhiyun orion_xor1_shared_resources[3].end = irq_1;
705*4882a593Smuzhiyun
706*4882a593Smuzhiyun dma_cap_set(DMA_MEMCPY, orion_xor1_channels_data[0].cap_mask);
707*4882a593Smuzhiyun dma_cap_set(DMA_XOR, orion_xor1_channels_data[0].cap_mask);
708*4882a593Smuzhiyun
709*4882a593Smuzhiyun dma_cap_set(DMA_MEMCPY, orion_xor1_channels_data[1].cap_mask);
710*4882a593Smuzhiyun dma_cap_set(DMA_XOR, orion_xor1_channels_data[1].cap_mask);
711*4882a593Smuzhiyun
712*4882a593Smuzhiyun platform_device_register(&orion_xor1_shared);
713*4882a593Smuzhiyun }
714*4882a593Smuzhiyun
715*4882a593Smuzhiyun /*****************************************************************************
716*4882a593Smuzhiyun * EHCI
717*4882a593Smuzhiyun ****************************************************************************/
718*4882a593Smuzhiyun static struct orion_ehci_data orion_ehci_data;
719*4882a593Smuzhiyun static u64 ehci_dmamask = DMA_BIT_MASK(32);
720*4882a593Smuzhiyun
721*4882a593Smuzhiyun
722*4882a593Smuzhiyun /*****************************************************************************
723*4882a593Smuzhiyun * EHCI0
724*4882a593Smuzhiyun ****************************************************************************/
725*4882a593Smuzhiyun static struct resource orion_ehci_resources[2];
726*4882a593Smuzhiyun
727*4882a593Smuzhiyun static struct platform_device orion_ehci = {
728*4882a593Smuzhiyun .name = "orion-ehci",
729*4882a593Smuzhiyun .id = 0,
730*4882a593Smuzhiyun .dev = {
731*4882a593Smuzhiyun .dma_mask = &ehci_dmamask,
732*4882a593Smuzhiyun .coherent_dma_mask = DMA_BIT_MASK(32),
733*4882a593Smuzhiyun .platform_data = &orion_ehci_data,
734*4882a593Smuzhiyun },
735*4882a593Smuzhiyun };
736*4882a593Smuzhiyun
orion_ehci_init(unsigned long mapbase,unsigned long irq,enum orion_ehci_phy_ver phy_version)737*4882a593Smuzhiyun void __init orion_ehci_init(unsigned long mapbase,
738*4882a593Smuzhiyun unsigned long irq,
739*4882a593Smuzhiyun enum orion_ehci_phy_ver phy_version)
740*4882a593Smuzhiyun {
741*4882a593Smuzhiyun orion_ehci_data.phy_version = phy_version;
742*4882a593Smuzhiyun fill_resources_irq(&orion_ehci, orion_ehci_resources, mapbase, SZ_4K - 1,
743*4882a593Smuzhiyun irq);
744*4882a593Smuzhiyun
745*4882a593Smuzhiyun platform_device_register(&orion_ehci);
746*4882a593Smuzhiyun }
747*4882a593Smuzhiyun
748*4882a593Smuzhiyun /*****************************************************************************
749*4882a593Smuzhiyun * EHCI1
750*4882a593Smuzhiyun ****************************************************************************/
751*4882a593Smuzhiyun static struct resource orion_ehci_1_resources[2];
752*4882a593Smuzhiyun
753*4882a593Smuzhiyun static struct platform_device orion_ehci_1 = {
754*4882a593Smuzhiyun .name = "orion-ehci",
755*4882a593Smuzhiyun .id = 1,
756*4882a593Smuzhiyun .dev = {
757*4882a593Smuzhiyun .dma_mask = &ehci_dmamask,
758*4882a593Smuzhiyun .coherent_dma_mask = DMA_BIT_MASK(32),
759*4882a593Smuzhiyun .platform_data = &orion_ehci_data,
760*4882a593Smuzhiyun },
761*4882a593Smuzhiyun };
762*4882a593Smuzhiyun
orion_ehci_1_init(unsigned long mapbase,unsigned long irq)763*4882a593Smuzhiyun void __init orion_ehci_1_init(unsigned long mapbase,
764*4882a593Smuzhiyun unsigned long irq)
765*4882a593Smuzhiyun {
766*4882a593Smuzhiyun fill_resources_irq(&orion_ehci_1, orion_ehci_1_resources,
767*4882a593Smuzhiyun mapbase, SZ_4K - 1, irq);
768*4882a593Smuzhiyun
769*4882a593Smuzhiyun platform_device_register(&orion_ehci_1);
770*4882a593Smuzhiyun }
771*4882a593Smuzhiyun
772*4882a593Smuzhiyun /*****************************************************************************
773*4882a593Smuzhiyun * EHCI2
774*4882a593Smuzhiyun ****************************************************************************/
775*4882a593Smuzhiyun static struct resource orion_ehci_2_resources[2];
776*4882a593Smuzhiyun
777*4882a593Smuzhiyun static struct platform_device orion_ehci_2 = {
778*4882a593Smuzhiyun .name = "orion-ehci",
779*4882a593Smuzhiyun .id = 2,
780*4882a593Smuzhiyun .dev = {
781*4882a593Smuzhiyun .dma_mask = &ehci_dmamask,
782*4882a593Smuzhiyun .coherent_dma_mask = DMA_BIT_MASK(32),
783*4882a593Smuzhiyun .platform_data = &orion_ehci_data,
784*4882a593Smuzhiyun },
785*4882a593Smuzhiyun };
786*4882a593Smuzhiyun
orion_ehci_2_init(unsigned long mapbase,unsigned long irq)787*4882a593Smuzhiyun void __init orion_ehci_2_init(unsigned long mapbase,
788*4882a593Smuzhiyun unsigned long irq)
789*4882a593Smuzhiyun {
790*4882a593Smuzhiyun fill_resources_irq(&orion_ehci_2, orion_ehci_2_resources,
791*4882a593Smuzhiyun mapbase, SZ_4K - 1, irq);
792*4882a593Smuzhiyun
793*4882a593Smuzhiyun platform_device_register(&orion_ehci_2);
794*4882a593Smuzhiyun }
795*4882a593Smuzhiyun
796*4882a593Smuzhiyun /*****************************************************************************
797*4882a593Smuzhiyun * SATA
798*4882a593Smuzhiyun ****************************************************************************/
799*4882a593Smuzhiyun static struct resource orion_sata_resources[2] = {
800*4882a593Smuzhiyun {
801*4882a593Smuzhiyun .name = "sata base",
802*4882a593Smuzhiyun }, {
803*4882a593Smuzhiyun .name = "sata irq",
804*4882a593Smuzhiyun },
805*4882a593Smuzhiyun };
806*4882a593Smuzhiyun
807*4882a593Smuzhiyun static struct platform_device orion_sata = {
808*4882a593Smuzhiyun .name = "sata_mv",
809*4882a593Smuzhiyun .id = 0,
810*4882a593Smuzhiyun .dev = {
811*4882a593Smuzhiyun .coherent_dma_mask = DMA_BIT_MASK(32),
812*4882a593Smuzhiyun },
813*4882a593Smuzhiyun };
814*4882a593Smuzhiyun
orion_sata_init(struct mv_sata_platform_data * sata_data,unsigned long mapbase,unsigned long irq)815*4882a593Smuzhiyun void __init orion_sata_init(struct mv_sata_platform_data *sata_data,
816*4882a593Smuzhiyun unsigned long mapbase,
817*4882a593Smuzhiyun unsigned long irq)
818*4882a593Smuzhiyun {
819*4882a593Smuzhiyun orion_sata.dev.platform_data = sata_data;
820*4882a593Smuzhiyun fill_resources_irq(&orion_sata, orion_sata_resources,
821*4882a593Smuzhiyun mapbase, 0x5000 - 1, irq);
822*4882a593Smuzhiyun
823*4882a593Smuzhiyun platform_device_register(&orion_sata);
824*4882a593Smuzhiyun }
825*4882a593Smuzhiyun
826*4882a593Smuzhiyun /*****************************************************************************
827*4882a593Smuzhiyun * Cryptographic Engines and Security Accelerator (CESA)
828*4882a593Smuzhiyun ****************************************************************************/
829*4882a593Smuzhiyun static struct resource orion_crypto_resources[] = {
830*4882a593Smuzhiyun {
831*4882a593Smuzhiyun .name = "regs",
832*4882a593Smuzhiyun }, {
833*4882a593Smuzhiyun .name = "crypto interrupt",
834*4882a593Smuzhiyun }, {
835*4882a593Smuzhiyun .name = "sram",
836*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
837*4882a593Smuzhiyun },
838*4882a593Smuzhiyun };
839*4882a593Smuzhiyun
840*4882a593Smuzhiyun static struct platform_device orion_crypto = {
841*4882a593Smuzhiyun .name = "mv_crypto",
842*4882a593Smuzhiyun .id = -1,
843*4882a593Smuzhiyun };
844*4882a593Smuzhiyun
orion_crypto_init(unsigned long mapbase,unsigned long srambase,unsigned long sram_size,unsigned long irq)845*4882a593Smuzhiyun void __init orion_crypto_init(unsigned long mapbase,
846*4882a593Smuzhiyun unsigned long srambase,
847*4882a593Smuzhiyun unsigned long sram_size,
848*4882a593Smuzhiyun unsigned long irq)
849*4882a593Smuzhiyun {
850*4882a593Smuzhiyun fill_resources_irq(&orion_crypto, orion_crypto_resources,
851*4882a593Smuzhiyun mapbase, 0xffff, irq);
852*4882a593Smuzhiyun orion_crypto.num_resources = 3;
853*4882a593Smuzhiyun orion_crypto_resources[2].start = srambase;
854*4882a593Smuzhiyun orion_crypto_resources[2].end = srambase + sram_size - 1;
855*4882a593Smuzhiyun
856*4882a593Smuzhiyun platform_device_register(&orion_crypto);
857*4882a593Smuzhiyun }
858