1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * OMAP 32ksynctimer/counter_32k-related code
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2009 Texas Instruments
6*4882a593Smuzhiyun * Copyright (C) 2010 Nokia Corporation
7*4882a593Smuzhiyun * Tony Lindgren <tony@atomide.com>
8*4882a593Smuzhiyun * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * NOTE: This timer is not the same timer as the old OMAP1 MPU timer.
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/init.h>
14*4882a593Smuzhiyun #include <linux/clk.h>
15*4882a593Smuzhiyun #include <linux/err.h>
16*4882a593Smuzhiyun #include <linux/io.h>
17*4882a593Smuzhiyun #include <linux/clocksource.h>
18*4882a593Smuzhiyun #include <linux/sched_clock.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #include <asm/mach/time.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #include <plat/counter-32k.h>
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */
25*4882a593Smuzhiyun #define OMAP2_32KSYNCNT_REV_OFF 0x0
26*4882a593Smuzhiyun #define OMAP2_32KSYNCNT_REV_SCHEME (0x3 << 30)
27*4882a593Smuzhiyun #define OMAP2_32KSYNCNT_CR_OFF_LOW 0x10
28*4882a593Smuzhiyun #define OMAP2_32KSYNCNT_CR_OFF_HIGH 0x30
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /*
31*4882a593Smuzhiyun * 32KHz clocksource ... always available, on pretty most chips except
32*4882a593Smuzhiyun * OMAP 730 and 1510. Other timers could be used as clocksources, with
33*4882a593Smuzhiyun * higher resolution in free-running counter modes (e.g. 12 MHz xtal),
34*4882a593Smuzhiyun * but systems won't necessarily want to spend resources that way.
35*4882a593Smuzhiyun */
36*4882a593Smuzhiyun static void __iomem *sync32k_cnt_reg;
37*4882a593Smuzhiyun
omap_32k_read_sched_clock(void)38*4882a593Smuzhiyun static u64 notrace omap_32k_read_sched_clock(void)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun return sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0;
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun /**
44*4882a593Smuzhiyun * omap_read_persistent_clock64 - Return time from a persistent clock.
45*4882a593Smuzhiyun *
46*4882a593Smuzhiyun * Reads the time from a source which isn't disabled during PM, the
47*4882a593Smuzhiyun * 32k sync timer. Convert the cycles elapsed since last read into
48*4882a593Smuzhiyun * nsecs and adds to a monotonically increasing timespec64.
49*4882a593Smuzhiyun */
50*4882a593Smuzhiyun static struct timespec64 persistent_ts;
51*4882a593Smuzhiyun static cycles_t cycles;
52*4882a593Smuzhiyun static unsigned int persistent_mult, persistent_shift;
53*4882a593Smuzhiyun
omap_read_persistent_clock64(struct timespec64 * ts)54*4882a593Smuzhiyun static void omap_read_persistent_clock64(struct timespec64 *ts)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun unsigned long long nsecs;
57*4882a593Smuzhiyun cycles_t last_cycles;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun last_cycles = cycles;
60*4882a593Smuzhiyun cycles = sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun nsecs = clocksource_cyc2ns(cycles - last_cycles,
63*4882a593Smuzhiyun persistent_mult, persistent_shift);
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun timespec64_add_ns(&persistent_ts, nsecs);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun *ts = persistent_ts;
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun /**
71*4882a593Smuzhiyun * omap_init_clocksource_32k - setup and register counter 32k as a
72*4882a593Smuzhiyun * kernel clocksource
73*4882a593Smuzhiyun * @pbase: base addr of counter_32k module
74*4882a593Smuzhiyun * @size: size of counter_32k to map
75*4882a593Smuzhiyun *
76*4882a593Smuzhiyun * Returns 0 upon success or negative error code upon failure.
77*4882a593Smuzhiyun *
78*4882a593Smuzhiyun */
omap_init_clocksource_32k(void __iomem * vbase)79*4882a593Smuzhiyun int __init omap_init_clocksource_32k(void __iomem *vbase)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun int ret;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun /*
84*4882a593Smuzhiyun * 32k sync Counter IP register offsets vary between the
85*4882a593Smuzhiyun * highlander version and the legacy ones.
86*4882a593Smuzhiyun * The 'SCHEME' bits(30-31) of the revision register is used
87*4882a593Smuzhiyun * to identify the version.
88*4882a593Smuzhiyun */
89*4882a593Smuzhiyun if (readl_relaxed(vbase + OMAP2_32KSYNCNT_REV_OFF) &
90*4882a593Smuzhiyun OMAP2_32KSYNCNT_REV_SCHEME)
91*4882a593Smuzhiyun sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_HIGH;
92*4882a593Smuzhiyun else
93*4882a593Smuzhiyun sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_LOW;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun /*
96*4882a593Smuzhiyun * 120000 rough estimate from the calculations in
97*4882a593Smuzhiyun * __clocksource_update_freq_scale.
98*4882a593Smuzhiyun */
99*4882a593Smuzhiyun clocks_calc_mult_shift(&persistent_mult, &persistent_shift,
100*4882a593Smuzhiyun 32768, NSEC_PER_SEC, 120000);
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun ret = clocksource_mmio_init(sync32k_cnt_reg, "32k_counter", 32768,
103*4882a593Smuzhiyun 250, 32, clocksource_mmio_readl_up);
104*4882a593Smuzhiyun if (ret) {
105*4882a593Smuzhiyun pr_err("32k_counter: can't register clocksource\n");
106*4882a593Smuzhiyun return ret;
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun sched_clock_register(omap_32k_read_sched_clock, 32, 32768);
110*4882a593Smuzhiyun register_persistent_clock(omap_read_persistent_clock64);
111*4882a593Smuzhiyun pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n");
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun return 0;
114*4882a593Smuzhiyun }
115