1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun NetWinder Floating Point Emulator 4*4882a593Smuzhiyun (c) Rebel.com, 1998-1999 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun Direct questions, comments to Scott Bambrough <scottb@netwinder.org> 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __FPSR_H__ 11*4882a593Smuzhiyun #define __FPSR_H__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* 14*4882a593Smuzhiyun The FPSR is a 32 bit register consisting of 4 parts, each exactly 15*4882a593Smuzhiyun one byte. 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun SYSTEM ID 18*4882a593Smuzhiyun EXCEPTION TRAP ENABLE BYTE 19*4882a593Smuzhiyun SYSTEM CONTROL BYTE 20*4882a593Smuzhiyun CUMULATIVE EXCEPTION FLAGS BYTE 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun The FPCR is a 32 bit register consisting of bit flags. 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* SYSTEM ID 26*4882a593Smuzhiyun ------------ 27*4882a593Smuzhiyun Note: the system id byte is read only */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun typedef unsigned int FPSR; /* type for floating point status register */ 30*4882a593Smuzhiyun typedef unsigned int FPCR; /* type for floating point control register */ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define MASK_SYSID 0xff000000 33*4882a593Smuzhiyun #define BIT_HARDWARE 0x80000000 34*4882a593Smuzhiyun #define FP_EMULATOR 0x01000000 /* System ID for emulator */ 35*4882a593Smuzhiyun #define FP_ACCELERATOR 0x81000000 /* System ID for FPA11 */ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* EXCEPTION TRAP ENABLE BYTE 38*4882a593Smuzhiyun ----------------------------- */ 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define MASK_TRAP_ENABLE 0x00ff0000 41*4882a593Smuzhiyun #define MASK_TRAP_ENABLE_STRICT 0x001f0000 42*4882a593Smuzhiyun #define BIT_IXE 0x00100000 /* inexact exception enable */ 43*4882a593Smuzhiyun #define BIT_UFE 0x00080000 /* underflow exception enable */ 44*4882a593Smuzhiyun #define BIT_OFE 0x00040000 /* overflow exception enable */ 45*4882a593Smuzhiyun #define BIT_DZE 0x00020000 /* divide by zero exception enable */ 46*4882a593Smuzhiyun #define BIT_IOE 0x00010000 /* invalid operation exception enable */ 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* SYSTEM CONTROL BYTE 49*4882a593Smuzhiyun ---------------------- */ 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define MASK_SYSTEM_CONTROL 0x0000ff00 52*4882a593Smuzhiyun #define MASK_TRAP_STRICT 0x00001f00 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define BIT_AC 0x00001000 /* use alternative C-flag definition 55*4882a593Smuzhiyun for compares */ 56*4882a593Smuzhiyun #define BIT_EP 0x00000800 /* use expanded packed decimal format */ 57*4882a593Smuzhiyun #define BIT_SO 0x00000400 /* select synchronous operation of FPA */ 58*4882a593Smuzhiyun #define BIT_NE 0x00000200 /* NaN exception bit */ 59*4882a593Smuzhiyun #define BIT_ND 0x00000100 /* no denormalized numbers bit */ 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* CUMULATIVE EXCEPTION FLAGS BYTE 62*4882a593Smuzhiyun ---------------------------------- */ 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define MASK_EXCEPTION_FLAGS 0x000000ff 65*4882a593Smuzhiyun #define MASK_EXCEPTION_FLAGS_STRICT 0x0000001f 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define BIT_IXC 0x00000010 /* inexact exception flag */ 68*4882a593Smuzhiyun #define BIT_UFC 0x00000008 /* underflow exception flag */ 69*4882a593Smuzhiyun #define BIT_OFC 0x00000004 /* overfloat exception flag */ 70*4882a593Smuzhiyun #define BIT_DZC 0x00000002 /* divide by zero exception flag */ 71*4882a593Smuzhiyun #define BIT_IOC 0x00000001 /* invalid operation exception flag */ 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* Floating Point Control Register 74*4882a593Smuzhiyun ----------------------------------*/ 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define BIT_RU 0x80000000 /* rounded up bit */ 77*4882a593Smuzhiyun #define BIT_IE 0x10000000 /* inexact bit */ 78*4882a593Smuzhiyun #define BIT_MO 0x08000000 /* mantissa overflow bit */ 79*4882a593Smuzhiyun #define BIT_EO 0x04000000 /* exponent overflow bit */ 80*4882a593Smuzhiyun #define BIT_SB 0x00000800 /* store bounce */ 81*4882a593Smuzhiyun #define BIT_AB 0x00000400 /* arithmetic bounce */ 82*4882a593Smuzhiyun #define BIT_RE 0x00000200 /* rounding exception */ 83*4882a593Smuzhiyun #define BIT_DA 0x00000100 /* disable FPA */ 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define MASK_OP 0x00f08010 /* AU operation code */ 86*4882a593Smuzhiyun #define MASK_PR 0x00080080 /* AU precision */ 87*4882a593Smuzhiyun #define MASK_S1 0x00070000 /* AU source register 1 */ 88*4882a593Smuzhiyun #define MASK_S2 0x00000007 /* AU source register 2 */ 89*4882a593Smuzhiyun #define MASK_DS 0x00007000 /* AU destination register */ 90*4882a593Smuzhiyun #define MASK_RM 0x00000060 /* AU rounding mode */ 91*4882a593Smuzhiyun #define MASK_ALU 0x9cfff2ff /* only ALU can write these bits */ 92*4882a593Smuzhiyun #define MASK_RESET 0x00000d00 /* bits set on reset, all others cleared */ 93*4882a593Smuzhiyun #define MASK_WFC MASK_RESET 94*4882a593Smuzhiyun #define MASK_RFC ~MASK_RESET 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun #endif 97