1*4882a593Smuzhiyun/* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * linux/arch/arm/mm/tlb-v7.S 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 1997-2002 Russell King 6*4882a593Smuzhiyun * Modified for ARMv7 by Catalin Marinas 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * ARM architecture version 6 TLB handling functions. 9*4882a593Smuzhiyun * These assume a split I/D TLB. 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun#include <linux/init.h> 12*4882a593Smuzhiyun#include <linux/linkage.h> 13*4882a593Smuzhiyun#include <asm/assembler.h> 14*4882a593Smuzhiyun#include <asm/asm-offsets.h> 15*4882a593Smuzhiyun#include <asm/page.h> 16*4882a593Smuzhiyun#include <asm/tlbflush.h> 17*4882a593Smuzhiyun#include "proc-macros.S" 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun/* 20*4882a593Smuzhiyun * v7wbi_flush_user_tlb_range(start, end, vma) 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * Invalidate a range of TLB entries in the specified address space. 23*4882a593Smuzhiyun * 24*4882a593Smuzhiyun * - start - start address (may not be aligned) 25*4882a593Smuzhiyun * - end - end address (exclusive, may not be aligned) 26*4882a593Smuzhiyun * - vma - vma_struct describing address range 27*4882a593Smuzhiyun * 28*4882a593Smuzhiyun * It is assumed that: 29*4882a593Smuzhiyun * - the "Invalidate single entry" instruction will invalidate 30*4882a593Smuzhiyun * both the I and the D TLBs on Harvard-style TLBs 31*4882a593Smuzhiyun */ 32*4882a593SmuzhiyunENTRY(v7wbi_flush_user_tlb_range) 33*4882a593Smuzhiyun vma_vm_mm r3, r2 @ get vma->vm_mm 34*4882a593Smuzhiyun mmid r3, r3 @ get vm_mm->context.id 35*4882a593Smuzhiyun dsb ish 36*4882a593Smuzhiyun mov r0, r0, lsr #PAGE_SHIFT @ align address 37*4882a593Smuzhiyun mov r1, r1, lsr #PAGE_SHIFT 38*4882a593Smuzhiyun asid r3, r3 @ mask ASID 39*4882a593Smuzhiyun#ifdef CONFIG_ARM_ERRATA_720789 40*4882a593Smuzhiyun ALT_SMP(W(mov) r3, #0 ) 41*4882a593Smuzhiyun ALT_UP(W(nop) ) 42*4882a593Smuzhiyun#endif 43*4882a593Smuzhiyun orr r0, r3, r0, lsl #PAGE_SHIFT @ Create initial MVA 44*4882a593Smuzhiyun mov r1, r1, lsl #PAGE_SHIFT 45*4882a593Smuzhiyun1: 46*4882a593Smuzhiyun#ifdef CONFIG_ARM_ERRATA_720789 47*4882a593Smuzhiyun ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable) 48*4882a593Smuzhiyun#else 49*4882a593Smuzhiyun ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable) 50*4882a593Smuzhiyun#endif 51*4882a593Smuzhiyun ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun add r0, r0, #PAGE_SZ 54*4882a593Smuzhiyun cmp r0, r1 55*4882a593Smuzhiyun blo 1b 56*4882a593Smuzhiyun dsb ish 57*4882a593Smuzhiyun ret lr 58*4882a593SmuzhiyunENDPROC(v7wbi_flush_user_tlb_range) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun/* 61*4882a593Smuzhiyun * v7wbi_flush_kern_tlb_range(start,end) 62*4882a593Smuzhiyun * 63*4882a593Smuzhiyun * Invalidate a range of kernel TLB entries 64*4882a593Smuzhiyun * 65*4882a593Smuzhiyun * - start - start address (may not be aligned) 66*4882a593Smuzhiyun * - end - end address (exclusive, may not be aligned) 67*4882a593Smuzhiyun */ 68*4882a593SmuzhiyunENTRY(v7wbi_flush_kern_tlb_range) 69*4882a593Smuzhiyun dsb ish 70*4882a593Smuzhiyun mov r0, r0, lsr #PAGE_SHIFT @ align address 71*4882a593Smuzhiyun mov r1, r1, lsr #PAGE_SHIFT 72*4882a593Smuzhiyun mov r0, r0, lsl #PAGE_SHIFT 73*4882a593Smuzhiyun mov r1, r1, lsl #PAGE_SHIFT 74*4882a593Smuzhiyun1: 75*4882a593Smuzhiyun#ifdef CONFIG_ARM_ERRATA_720789 76*4882a593Smuzhiyun ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable) 77*4882a593Smuzhiyun#else 78*4882a593Smuzhiyun ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable) 79*4882a593Smuzhiyun#endif 80*4882a593Smuzhiyun ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA 81*4882a593Smuzhiyun add r0, r0, #PAGE_SZ 82*4882a593Smuzhiyun cmp r0, r1 83*4882a593Smuzhiyun blo 1b 84*4882a593Smuzhiyun dsb ish 85*4882a593Smuzhiyun isb 86*4882a593Smuzhiyun ret lr 87*4882a593SmuzhiyunENDPROC(v7wbi_flush_kern_tlb_range) 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun __INIT 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */ 92*4882a593Smuzhiyun define_tlb_functions v7wbi, v7wbi_tlb_flags_up, flags_smp=v7wbi_tlb_flags_smp 93