1*4882a593Smuzhiyun/* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2015 Russell King 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This assembly is required to safely remap the physical address space 6*4882a593Smuzhiyun * for Keystone 2 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun#include <linux/linkage.h> 9*4882a593Smuzhiyun#include <linux/pgtable.h> 10*4882a593Smuzhiyun#include <asm/asm-offsets.h> 11*4882a593Smuzhiyun#include <asm/cp15.h> 12*4882a593Smuzhiyun#include <asm/memory.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun .section ".idmap.text", "ax" 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun#define L1_ORDER 3 17*4882a593Smuzhiyun#define L2_ORDER 3 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunENTRY(lpae_pgtables_remap_asm) 20*4882a593Smuzhiyun stmfd sp!, {r4-r8, lr} 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun mrc p15, 0, r8, c1, c0, 0 @ read control reg 23*4882a593Smuzhiyun bic ip, r8, #CR_M @ disable caches and MMU 24*4882a593Smuzhiyun mcr p15, 0, ip, c1, c0, 0 25*4882a593Smuzhiyun dsb 26*4882a593Smuzhiyun isb 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* Update level 2 entries covering the kernel */ 29*4882a593Smuzhiyun ldr r6, =(_end - 1) 30*4882a593Smuzhiyun add r7, r2, #0x1000 31*4882a593Smuzhiyun add r6, r7, r6, lsr #SECTION_SHIFT - L2_ORDER 32*4882a593Smuzhiyun add r7, r7, #PAGE_OFFSET >> (SECTION_SHIFT - L2_ORDER) 33*4882a593Smuzhiyun1: ldrd r4, r5, [r7] 34*4882a593Smuzhiyun adds r4, r4, r0 35*4882a593Smuzhiyun adc r5, r5, r1 36*4882a593Smuzhiyun strd r4, r5, [r7], #1 << L2_ORDER 37*4882a593Smuzhiyun cmp r7, r6 38*4882a593Smuzhiyun bls 1b 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* Update level 2 entries for the boot data */ 41*4882a593Smuzhiyun add r7, r2, #0x1000 42*4882a593Smuzhiyun movw r3, #FDT_FIXED_BASE >> (SECTION_SHIFT - L2_ORDER) 43*4882a593Smuzhiyun add r7, r7, r3 44*4882a593Smuzhiyun ldrd r4, r5, [r7] 45*4882a593Smuzhiyun adds r4, r4, r0 46*4882a593Smuzhiyun adc r5, r5, r1 47*4882a593Smuzhiyun strd r4, r5, [r7], #1 << L2_ORDER 48*4882a593Smuzhiyun ldrd r4, r5, [r7] 49*4882a593Smuzhiyun adds r4, r4, r0 50*4882a593Smuzhiyun adc r5, r5, r1 51*4882a593Smuzhiyun strd r4, r5, [r7] 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* Update level 1 entries */ 54*4882a593Smuzhiyun mov r6, #4 55*4882a593Smuzhiyun mov r7, r2 56*4882a593Smuzhiyun2: ldrd r4, r5, [r7] 57*4882a593Smuzhiyun adds r4, r4, r0 58*4882a593Smuzhiyun adc r5, r5, r1 59*4882a593Smuzhiyun strd r4, r5, [r7], #1 << L1_ORDER 60*4882a593Smuzhiyun subs r6, r6, #1 61*4882a593Smuzhiyun bne 2b 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun mrrc p15, 0, r4, r5, c2 @ read TTBR0 64*4882a593Smuzhiyun adds r4, r4, r0 @ update physical address 65*4882a593Smuzhiyun adc r5, r5, r1 66*4882a593Smuzhiyun mcrr p15, 0, r4, r5, c2 @ write back TTBR0 67*4882a593Smuzhiyun mrrc p15, 1, r4, r5, c2 @ read TTBR1 68*4882a593Smuzhiyun adds r4, r4, r0 @ update physical address 69*4882a593Smuzhiyun adc r5, r5, r1 70*4882a593Smuzhiyun mcrr p15, 1, r4, r5, c2 @ write back TTBR1 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun dsb 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun mov ip, #0 75*4882a593Smuzhiyun mcr p15, 0, ip, c7, c5, 0 @ I+BTB cache invalidate 76*4882a593Smuzhiyun mcr p15, 0, ip, c8, c7, 0 @ local_flush_tlb_all() 77*4882a593Smuzhiyun dsb 78*4882a593Smuzhiyun isb 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun mcr p15, 0, r8, c1, c0, 0 @ re-enable MMU 81*4882a593Smuzhiyun dsb 82*4882a593Smuzhiyun isb 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun ldmfd sp!, {r4-r8, pc} 85*4882a593SmuzhiyunENDPROC(lpae_pgtables_remap_asm) 86