1*4882a593Smuzhiyun/* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * arch/arm/mm/proc-v7-2level.S 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2001 Deep Blue Solutions Ltd. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#define TTB_S (1 << 1) 9*4882a593Smuzhiyun#define TTB_RGN_NC (0 << 3) 10*4882a593Smuzhiyun#define TTB_RGN_OC_WBWA (1 << 3) 11*4882a593Smuzhiyun#define TTB_RGN_OC_WT (2 << 3) 12*4882a593Smuzhiyun#define TTB_RGN_OC_WB (3 << 3) 13*4882a593Smuzhiyun#define TTB_NOS (1 << 5) 14*4882a593Smuzhiyun#define TTB_IRGN_NC ((0 << 0) | (0 << 6)) 15*4882a593Smuzhiyun#define TTB_IRGN_WBWA ((0 << 0) | (1 << 6)) 16*4882a593Smuzhiyun#define TTB_IRGN_WT ((1 << 0) | (0 << 6)) 17*4882a593Smuzhiyun#define TTB_IRGN_WB ((1 << 0) | (1 << 6)) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun/* PTWs cacheable, inner WB not shareable, outer WB not shareable */ 20*4882a593Smuzhiyun#define TTB_FLAGS_UP TTB_IRGN_WB|TTB_RGN_OC_WB 21*4882a593Smuzhiyun#define PMD_FLAGS_UP PMD_SECT_WB 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */ 24*4882a593Smuzhiyun#define TTB_FLAGS_SMP TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA 25*4882a593Smuzhiyun#define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun/* 28*4882a593Smuzhiyun * cpu_v7_switch_mm(pgd_phys, tsk) 29*4882a593Smuzhiyun * 30*4882a593Smuzhiyun * Set the translation table base pointer to be pgd_phys 31*4882a593Smuzhiyun * 32*4882a593Smuzhiyun * - pgd_phys - physical address of new TTB 33*4882a593Smuzhiyun * 34*4882a593Smuzhiyun * It is assumed that: 35*4882a593Smuzhiyun * - we are not using split page tables 36*4882a593Smuzhiyun * 37*4882a593Smuzhiyun * Note that we always need to flush BTAC/BTB if IBE is set 38*4882a593Smuzhiyun * even on Cortex-A8 revisions not affected by 430973. 39*4882a593Smuzhiyun * If IBE is not set, the flush BTAC/BTB won't do anything. 40*4882a593Smuzhiyun */ 41*4882a593SmuzhiyunENTRY(cpu_v7_switch_mm) 42*4882a593Smuzhiyun#ifdef CONFIG_MMU 43*4882a593Smuzhiyun mmid r1, r1 @ get mm->context.id 44*4882a593Smuzhiyun ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP) 45*4882a593Smuzhiyun ALT_UP(orr r0, r0, #TTB_FLAGS_UP) 46*4882a593Smuzhiyun#ifdef CONFIG_PID_IN_CONTEXTIDR 47*4882a593Smuzhiyun mrc p15, 0, r2, c13, c0, 1 @ read current context ID 48*4882a593Smuzhiyun lsr r2, r2, #8 @ extract the PID 49*4882a593Smuzhiyun bfi r1, r2, #8, #24 @ insert into new context ID 50*4882a593Smuzhiyun#endif 51*4882a593Smuzhiyun#ifdef CONFIG_ARM_ERRATA_754322 52*4882a593Smuzhiyun dsb 53*4882a593Smuzhiyun#endif 54*4882a593Smuzhiyun mcr p15, 0, r1, c13, c0, 1 @ set context ID 55*4882a593Smuzhiyun isb 56*4882a593Smuzhiyun mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 57*4882a593Smuzhiyun isb 58*4882a593Smuzhiyun#endif 59*4882a593Smuzhiyun bx lr 60*4882a593SmuzhiyunENDPROC(cpu_v7_switch_mm) 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun/* 63*4882a593Smuzhiyun * cpu_v7_set_pte_ext(ptep, pte) 64*4882a593Smuzhiyun * 65*4882a593Smuzhiyun * Set a level 2 translation table entry. 66*4882a593Smuzhiyun * 67*4882a593Smuzhiyun * - ptep - pointer to level 2 translation table entry 68*4882a593Smuzhiyun * (hardware version is stored at +2048 bytes) 69*4882a593Smuzhiyun * - pte - PTE value to store 70*4882a593Smuzhiyun * - ext - value for extended PTE bits 71*4882a593Smuzhiyun */ 72*4882a593SmuzhiyunENTRY(cpu_v7_set_pte_ext) 73*4882a593Smuzhiyun#ifdef CONFIG_MMU 74*4882a593Smuzhiyun str r1, [r0] @ linux version 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun bic r3, r1, #0x000003f0 77*4882a593Smuzhiyun bic r3, r3, #PTE_TYPE_MASK 78*4882a593Smuzhiyun orr r3, r3, r2 79*4882a593Smuzhiyun orr r3, r3, #PTE_EXT_AP0 | 2 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun tst r1, #1 << 4 82*4882a593Smuzhiyun orrne r3, r3, #PTE_EXT_TEX(1) 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun eor r1, r1, #L_PTE_DIRTY 85*4882a593Smuzhiyun tst r1, #L_PTE_RDONLY | L_PTE_DIRTY 86*4882a593Smuzhiyun orrne r3, r3, #PTE_EXT_APX 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun tst r1, #L_PTE_USER 89*4882a593Smuzhiyun orrne r3, r3, #PTE_EXT_AP1 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun tst r1, #L_PTE_XN 92*4882a593Smuzhiyun orrne r3, r3, #PTE_EXT_XN 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun tst r1, #L_PTE_YOUNG 95*4882a593Smuzhiyun tstne r1, #L_PTE_VALID 96*4882a593Smuzhiyun eorne r1, r1, #L_PTE_NONE 97*4882a593Smuzhiyun tstne r1, #L_PTE_NONE 98*4882a593Smuzhiyun moveq r3, #0 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun ARM( str r3, [r0, #2048]! ) 101*4882a593Smuzhiyun THUMB( add r0, r0, #2048 ) 102*4882a593Smuzhiyun THUMB( str r3, [r0] ) 103*4882a593Smuzhiyun ALT_SMP(W(nop)) 104*4882a593Smuzhiyun ALT_UP (mcr p15, 0, r0, c7, c10, 1) @ flush_pte 105*4882a593Smuzhiyun#endif 106*4882a593Smuzhiyun bx lr 107*4882a593SmuzhiyunENDPROC(cpu_v7_set_pte_ext) 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun /* 110*4882a593Smuzhiyun * Memory region attributes with SCTLR.TRE=1 111*4882a593Smuzhiyun * 112*4882a593Smuzhiyun * n = TEX[0],C,B 113*4882a593Smuzhiyun * TR = PRRR[2n+1:2n] - memory type 114*4882a593Smuzhiyun * IR = NMRR[2n+1:2n] - inner cacheable property 115*4882a593Smuzhiyun * OR = NMRR[2n+17:2n+16] - outer cacheable property 116*4882a593Smuzhiyun * 117*4882a593Smuzhiyun * n TR IR OR 118*4882a593Smuzhiyun * UNCACHED 000 00 119*4882a593Smuzhiyun * BUFFERABLE 001 10 00 00 120*4882a593Smuzhiyun * WRITETHROUGH 010 10 10 10 121*4882a593Smuzhiyun * WRITEBACK 011 10 11 11 122*4882a593Smuzhiyun * reserved 110 123*4882a593Smuzhiyun * WRITEALLOC 111 10 01 01 124*4882a593Smuzhiyun * DEV_SHARED 100 01 125*4882a593Smuzhiyun * DEV_NONSHARED 100 01 126*4882a593Smuzhiyun * DEV_WC 001 10 127*4882a593Smuzhiyun * DEV_CACHED 011 10 128*4882a593Smuzhiyun * 129*4882a593Smuzhiyun * Other attributes: 130*4882a593Smuzhiyun * 131*4882a593Smuzhiyun * DS0 = PRRR[16] = 0 - device shareable property 132*4882a593Smuzhiyun * DS1 = PRRR[17] = 1 - device shareable property 133*4882a593Smuzhiyun * NS0 = PRRR[18] = 0 - normal shareable property 134*4882a593Smuzhiyun * NS1 = PRRR[19] = 1 - normal shareable property 135*4882a593Smuzhiyun * NOS = PRRR[24+n] = 1 - not outer shareable 136*4882a593Smuzhiyun */ 137*4882a593Smuzhiyun.equ PRRR, 0xff0a81a8 138*4882a593Smuzhiyun.equ NMRR, 0x40e040e0 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun /* 141*4882a593Smuzhiyun * Macro for setting up the TTBRx and TTBCR registers. 142*4882a593Smuzhiyun * - \ttb0 and \ttb1 updated with the corresponding flags. 143*4882a593Smuzhiyun */ 144*4882a593Smuzhiyun .macro v7_ttb_setup, zero, ttbr0l, ttbr0h, ttbr1, tmp 145*4882a593Smuzhiyun mcr p15, 0, \zero, c2, c0, 2 @ TTB control register 146*4882a593Smuzhiyun ALT_SMP(orr \ttbr0l, \ttbr0l, #TTB_FLAGS_SMP) 147*4882a593Smuzhiyun ALT_UP(orr \ttbr0l, \ttbr0l, #TTB_FLAGS_UP) 148*4882a593Smuzhiyun ALT_SMP(orr \ttbr1, \ttbr1, #TTB_FLAGS_SMP) 149*4882a593Smuzhiyun ALT_UP(orr \ttbr1, \ttbr1, #TTB_FLAGS_UP) 150*4882a593Smuzhiyun mcr p15, 0, \ttbr1, c2, c0, 1 @ load TTB1 151*4882a593Smuzhiyun .endm 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun /* AT 154*4882a593Smuzhiyun * TFR EV X F I D LR S 155*4882a593Smuzhiyun * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM 156*4882a593Smuzhiyun * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced 157*4882a593Smuzhiyun * 01 0 110 0011 1100 .111 1101 < we want 158*4882a593Smuzhiyun */ 159*4882a593Smuzhiyun .align 2 160*4882a593Smuzhiyun .type v7_crval, #object 161*4882a593Smuzhiyunv7_crval: 162*4882a593Smuzhiyun crval clear=0x2120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c 163