1*4882a593Smuzhiyun/* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * L2C-310 early resume code. This can be used by platforms to restore 4*4882a593Smuzhiyun * the settings of their L2 cache controller before restoring the 5*4882a593Smuzhiyun * processor state. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * This code can only be used to if you are running in the secure world. 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun#include <linux/linkage.h> 10*4882a593Smuzhiyun#include <asm/assembler.h> 11*4882a593Smuzhiyun#include <asm/hardware/cache-l2x0.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun .text 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunENTRY(l2c310_early_resume) 16*4882a593Smuzhiyun adr r0, 1f 17*4882a593Smuzhiyun ldr r2, [r0] 18*4882a593Smuzhiyun add r0, r2, r0 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun ldmia r0, {r1, r2, r3, r4, r5, r6, r7, r8} 21*4882a593Smuzhiyun @ r1 = phys address of L2C-310 controller 22*4882a593Smuzhiyun @ r2 = aux_ctrl 23*4882a593Smuzhiyun @ r3 = tag_latency 24*4882a593Smuzhiyun @ r4 = data_latency 25*4882a593Smuzhiyun @ r5 = filter_start 26*4882a593Smuzhiyun @ r6 = filter_end 27*4882a593Smuzhiyun @ r7 = prefetch_ctrl 28*4882a593Smuzhiyun @ r8 = pwr_ctrl 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun @ Check that the address has been initialised 31*4882a593Smuzhiyun teq r1, #0 32*4882a593Smuzhiyun reteq lr 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun @ The prefetch and power control registers are revision dependent 35*4882a593Smuzhiyun @ and can be written whether or not the L2 cache is enabled 36*4882a593Smuzhiyun ldr r0, [r1, #L2X0_CACHE_ID] 37*4882a593Smuzhiyun and r0, r0, #L2X0_CACHE_ID_RTL_MASK 38*4882a593Smuzhiyun cmp r0, #L310_CACHE_ID_RTL_R2P0 39*4882a593Smuzhiyun strcs r7, [r1, #L310_PREFETCH_CTRL] 40*4882a593Smuzhiyun cmp r0, #L310_CACHE_ID_RTL_R3P0 41*4882a593Smuzhiyun strcs r8, [r1, #L310_POWER_CTRL] 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun @ Don't setup the L2 cache if it is already enabled 44*4882a593Smuzhiyun ldr r0, [r1, #L2X0_CTRL] 45*4882a593Smuzhiyun tst r0, #L2X0_CTRL_EN 46*4882a593Smuzhiyun retne lr 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun str r3, [r1, #L310_TAG_LATENCY_CTRL] 49*4882a593Smuzhiyun str r4, [r1, #L310_DATA_LATENCY_CTRL] 50*4882a593Smuzhiyun str r6, [r1, #L310_ADDR_FILTER_END] 51*4882a593Smuzhiyun str r5, [r1, #L310_ADDR_FILTER_START] 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun str r2, [r1, #L2X0_AUX_CTRL] 54*4882a593Smuzhiyun mov r9, #L2X0_CTRL_EN 55*4882a593Smuzhiyun str r9, [r1, #L2X0_CTRL] 56*4882a593Smuzhiyun ret lr 57*4882a593SmuzhiyunENDPROC(l2c310_early_resume) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun .align 60*4882a593Smuzhiyun1: .long l2x0_saved_regs - . 61