1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Zynq power management 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2012 - 2014 Xilinx 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Sören Brinkmann <soren.brinkmann@xilinx.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <linux/io.h> 11*4882a593Smuzhiyun #include <linux/of_address.h> 12*4882a593Smuzhiyun #include <linux/of_device.h> 13*4882a593Smuzhiyun #include "common.h" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* register offsets */ 16*4882a593Smuzhiyun #define DDRC_CTRL_REG1_OFFS 0x60 17*4882a593Smuzhiyun #define DDRC_DRAM_PARAM_REG3_OFFS 0x20 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* bitfields */ 20*4882a593Smuzhiyun #define DDRC_CLOCKSTOP_MASK BIT(23) 21*4882a593Smuzhiyun #define DDRC_SELFREFRESH_MASK BIT(12) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun static void __iomem *ddrc_base; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /** 26*4882a593Smuzhiyun * zynq_pm_ioremap() - Create IO mappings 27*4882a593Smuzhiyun * @comp: DT compatible string 28*4882a593Smuzhiyun * Return: Pointer to the mapped memory or NULL. 29*4882a593Smuzhiyun * 30*4882a593Smuzhiyun * Remap the memory region for a compatible DT node. 31*4882a593Smuzhiyun */ zynq_pm_ioremap(const char * comp)32*4882a593Smuzhiyunstatic void __iomem *zynq_pm_ioremap(const char *comp) 33*4882a593Smuzhiyun { 34*4882a593Smuzhiyun struct device_node *np; 35*4882a593Smuzhiyun void __iomem *base = NULL; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun np = of_find_compatible_node(NULL, NULL, comp); 38*4882a593Smuzhiyun if (np) { 39*4882a593Smuzhiyun base = of_iomap(np, 0); 40*4882a593Smuzhiyun of_node_put(np); 41*4882a593Smuzhiyun } else { 42*4882a593Smuzhiyun pr_warn("%s: no compatible node found for '%s'\n", __func__, 43*4882a593Smuzhiyun comp); 44*4882a593Smuzhiyun } 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun return base; 47*4882a593Smuzhiyun } 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /** 50*4882a593Smuzhiyun * zynq_pm_late_init() - Power management init 51*4882a593Smuzhiyun * 52*4882a593Smuzhiyun * Initialization of power management related features and infrastructure. 53*4882a593Smuzhiyun */ zynq_pm_late_init(void)54*4882a593Smuzhiyunvoid __init zynq_pm_late_init(void) 55*4882a593Smuzhiyun { 56*4882a593Smuzhiyun u32 reg; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun ddrc_base = zynq_pm_ioremap("xlnx,zynq-ddrc-a05"); 59*4882a593Smuzhiyun if (!ddrc_base) { 60*4882a593Smuzhiyun pr_warn("%s: Unable to map DDRC IO memory.\n", __func__); 61*4882a593Smuzhiyun } else { 62*4882a593Smuzhiyun /* 63*4882a593Smuzhiyun * Enable DDRC clock stop feature. The HW takes care of 64*4882a593Smuzhiyun * entering/exiting the correct mode depending 65*4882a593Smuzhiyun * on activity state. 66*4882a593Smuzhiyun */ 67*4882a593Smuzhiyun reg = readl(ddrc_base + DDRC_DRAM_PARAM_REG3_OFFS); 68*4882a593Smuzhiyun reg |= DDRC_CLOCKSTOP_MASK; 69*4882a593Smuzhiyun writel(reg, ddrc_base + DDRC_DRAM_PARAM_REG3_OFFS); 70*4882a593Smuzhiyun } 71*4882a593Smuzhiyun } 72