1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * This file contains common function prototypes to avoid externs
4*4882a593Smuzhiyun * in the c files.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 2011 Xilinx
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #ifndef __MACH_ZYNQ_COMMON_H__
10*4882a593Smuzhiyun #define __MACH_ZYNQ_COMMON_H__
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun extern int zynq_slcr_init(void);
13*4882a593Smuzhiyun extern int zynq_early_slcr_init(void);
14*4882a593Smuzhiyun extern void zynq_slcr_cpu_stop(int cpu);
15*4882a593Smuzhiyun extern void zynq_slcr_cpu_start(int cpu);
16*4882a593Smuzhiyun extern bool zynq_slcr_cpu_state_read(int cpu);
17*4882a593Smuzhiyun extern void zynq_slcr_cpu_state_write(int cpu, bool die);
18*4882a593Smuzhiyun extern u32 zynq_slcr_get_device_id(void);
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #ifdef CONFIG_SMP
21*4882a593Smuzhiyun extern char zynq_secondary_trampoline;
22*4882a593Smuzhiyun extern char zynq_secondary_trampoline_jump;
23*4882a593Smuzhiyun extern char zynq_secondary_trampoline_end;
24*4882a593Smuzhiyun extern int zynq_cpun_start(u32 address, int cpu);
25*4882a593Smuzhiyun extern const struct smp_operations zynq_smp_ops;
26*4882a593Smuzhiyun #endif
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun extern void __iomem *zynq_scu_base;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun void zynq_pm_late_init(void);
31*4882a593Smuzhiyun
zynq_core_pm_init(void)32*4882a593Smuzhiyun static inline void zynq_core_pm_init(void)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun /* A9 clock gating */
35*4882a593Smuzhiyun asm volatile ("mrc p15, 0, r12, c15, c0, 0\n"
36*4882a593Smuzhiyun "orr r12, r12, #1\n"
37*4882a593Smuzhiyun "mcr p15, 0, r12, c15, c0, 0\n"
38*4882a593Smuzhiyun : /* no outputs */
39*4882a593Smuzhiyun : /* no inputs */
40*4882a593Smuzhiyun : "r12");
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun #endif
44