1*4882a593Smuzhiyun/* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * arch/arm/include/asm/dcscb_setup.S 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Created by: Dave Martin, 2012-06-22 6*4882a593Smuzhiyun * Copyright: (C) 2012-2013 Linaro Limited 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include <linux/linkage.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunENTRY(dcscb_power_up_setup) 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun cmp r0, #0 @ check affinity level 15*4882a593Smuzhiyun beq 2f 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun/* 18*4882a593Smuzhiyun * Enable cluster-level coherency, in preparation for turning on the MMU. 19*4882a593Smuzhiyun * The ACTLR SMP bit does not need to be set here, because cpu_resume() 20*4882a593Smuzhiyun * already restores that. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * A15/A7 may not require explicit L2 invalidation on reset, dependent 23*4882a593Smuzhiyun * on hardware integration decisions. 24*4882a593Smuzhiyun * For now, this code assumes that L2 is either already invalidated, 25*4882a593Smuzhiyun * or invalidation is not required. 26*4882a593Smuzhiyun */ 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun b cci_enable_port_for_self 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun2: @ Implementation-specific local CPU setup operations should go here, 31*4882a593Smuzhiyun @ if any. In this case, there is nothing to do. 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun bx lr 34*4882a593Smuzhiyun 35*4882a593SmuzhiyunENDPROC(dcscb_power_up_setup) 36