1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2002 ARM Ltd.
4*4882a593Smuzhiyun * Copyright (C) 2008 STMicroelctronics.
5*4882a593Smuzhiyun * Copyright (C) 2009 ST-Ericsson.
6*4882a593Smuzhiyun * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * This file is based on arm realview platform
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun #include <linux/init.h>
11*4882a593Smuzhiyun #include <linux/errno.h>
12*4882a593Smuzhiyun #include <linux/delay.h>
13*4882a593Smuzhiyun #include <linux/device.h>
14*4882a593Smuzhiyun #include <linux/smp.h>
15*4882a593Smuzhiyun #include <linux/io.h>
16*4882a593Smuzhiyun #include <linux/of.h>
17*4882a593Smuzhiyun #include <linux/of_address.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #include <asm/cacheflush.h>
20*4882a593Smuzhiyun #include <asm/smp_plat.h>
21*4882a593Smuzhiyun #include <asm/smp_scu.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #include "db8500-regs.h"
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /* Magic triggers in backup RAM */
26*4882a593Smuzhiyun #define UX500_CPU1_JUMPADDR_OFFSET 0x1FF4
27*4882a593Smuzhiyun #define UX500_CPU1_WAKEMAGIC_OFFSET 0x1FF0
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun static void __iomem *backupram;
30*4882a593Smuzhiyun
ux500_smp_prepare_cpus(unsigned int max_cpus)31*4882a593Smuzhiyun static void __init ux500_smp_prepare_cpus(unsigned int max_cpus)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun struct device_node *np;
34*4882a593Smuzhiyun static void __iomem *scu_base;
35*4882a593Smuzhiyun unsigned int ncores;
36*4882a593Smuzhiyun int i;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun np = of_find_compatible_node(NULL, NULL, "ste,dbx500-backupram");
39*4882a593Smuzhiyun if (!np) {
40*4882a593Smuzhiyun pr_err("No backupram base address\n");
41*4882a593Smuzhiyun return;
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun backupram = of_iomap(np, 0);
44*4882a593Smuzhiyun of_node_put(np);
45*4882a593Smuzhiyun if (!backupram) {
46*4882a593Smuzhiyun pr_err("No backupram remap\n");
47*4882a593Smuzhiyun return;
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
51*4882a593Smuzhiyun if (!np) {
52*4882a593Smuzhiyun pr_err("No SCU base address\n");
53*4882a593Smuzhiyun return;
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun scu_base = of_iomap(np, 0);
56*4882a593Smuzhiyun of_node_put(np);
57*4882a593Smuzhiyun if (!scu_base) {
58*4882a593Smuzhiyun pr_err("No SCU remap\n");
59*4882a593Smuzhiyun return;
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun scu_enable(scu_base);
63*4882a593Smuzhiyun ncores = scu_get_core_count(scu_base);
64*4882a593Smuzhiyun for (i = 0; i < ncores; i++)
65*4882a593Smuzhiyun set_cpu_possible(i, true);
66*4882a593Smuzhiyun iounmap(scu_base);
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun
ux500_boot_secondary(unsigned int cpu,struct task_struct * idle)69*4882a593Smuzhiyun static int ux500_boot_secondary(unsigned int cpu, struct task_struct *idle)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun /*
72*4882a593Smuzhiyun * write the address of secondary startup into the backup ram register
73*4882a593Smuzhiyun * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the
74*4882a593Smuzhiyun * backup ram register at offset 0x1FF0, which is what boot rom code
75*4882a593Smuzhiyun * is waiting for. This will wake up the secondary core from WFE.
76*4882a593Smuzhiyun */
77*4882a593Smuzhiyun writel(__pa_symbol(secondary_startup),
78*4882a593Smuzhiyun backupram + UX500_CPU1_JUMPADDR_OFFSET);
79*4882a593Smuzhiyun writel(0xA1FEED01,
80*4882a593Smuzhiyun backupram + UX500_CPU1_WAKEMAGIC_OFFSET);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /* make sure write buffer is drained */
83*4882a593Smuzhiyun mb();
84*4882a593Smuzhiyun arch_send_wakeup_ipi_mask(cpumask_of(cpu));
85*4882a593Smuzhiyun return 0;
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun #ifdef CONFIG_HOTPLUG_CPU
ux500_cpu_die(unsigned int cpu)89*4882a593Smuzhiyun void ux500_cpu_die(unsigned int cpu)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun wfi();
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun #endif
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun static const struct smp_operations ux500_smp_ops __initconst = {
96*4882a593Smuzhiyun .smp_prepare_cpus = ux500_smp_prepare_cpus,
97*4882a593Smuzhiyun .smp_boot_secondary = ux500_boot_secondary,
98*4882a593Smuzhiyun #ifdef CONFIG_HOTPLUG_CPU
99*4882a593Smuzhiyun .cpu_die = ux500_cpu_die,
100*4882a593Smuzhiyun #endif
101*4882a593Smuzhiyun };
102*4882a593Smuzhiyun CPU_METHOD_OF_DECLARE(ux500_smp, "ste,dbx500-smp", &ux500_smp_ops);
103