1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * NVIDIA Tegra SoC device tree board support
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2011, 2013, NVIDIA Corporation
6*4882a593Smuzhiyun * Copyright (C) 2010 Secret Lab Technologies, Ltd.
7*4882a593Smuzhiyun * Copyright (C) 2010 Google, Inc.
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/clk.h>
11*4882a593Smuzhiyun #include <linux/clk/tegra.h>
12*4882a593Smuzhiyun #include <linux/dma-mapping.h>
13*4882a593Smuzhiyun #include <linux/init.h>
14*4882a593Smuzhiyun #include <linux/io.h>
15*4882a593Smuzhiyun #include <linux/irqchip.h>
16*4882a593Smuzhiyun #include <linux/irqdomain.h>
17*4882a593Smuzhiyun #include <linux/kernel.h>
18*4882a593Smuzhiyun #include <linux/of_address.h>
19*4882a593Smuzhiyun #include <linux/of_fdt.h>
20*4882a593Smuzhiyun #include <linux/of.h>
21*4882a593Smuzhiyun #include <linux/of_platform.h>
22*4882a593Smuzhiyun #include <linux/pda_power.h>
23*4882a593Smuzhiyun #include <linux/platform_device.h>
24*4882a593Smuzhiyun #include <linux/serial_8250.h>
25*4882a593Smuzhiyun #include <linux/slab.h>
26*4882a593Smuzhiyun #include <linux/sys_soc.h>
27*4882a593Smuzhiyun #include <linux/usb/tegra_usb_phy.h>
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #include <linux/firmware/trusted_foundations.h>
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #include <soc/tegra/fuse.h>
32*4882a593Smuzhiyun #include <soc/tegra/pmc.h>
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #include <asm/firmware.h>
35*4882a593Smuzhiyun #include <asm/hardware/cache-l2x0.h>
36*4882a593Smuzhiyun #include <asm/mach/arch.h>
37*4882a593Smuzhiyun #include <asm/mach/time.h>
38*4882a593Smuzhiyun #include <asm/mach-types.h>
39*4882a593Smuzhiyun #include <asm/psci.h>
40*4882a593Smuzhiyun #include <asm/setup.h>
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun #include "board.h"
43*4882a593Smuzhiyun #include "common.h"
44*4882a593Smuzhiyun #include "iomap.h"
45*4882a593Smuzhiyun #include "pm.h"
46*4882a593Smuzhiyun #include "reset.h"
47*4882a593Smuzhiyun #include "sleep.h"
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /*
50*4882a593Smuzhiyun * Storage for debug-macro.S's state.
51*4882a593Smuzhiyun *
52*4882a593Smuzhiyun * This must be in .data not .bss so that it gets initialized each time the
53*4882a593Smuzhiyun * kernel is loaded. The data is declared here rather than debug-macro.S so
54*4882a593Smuzhiyun * that multiple inclusions of debug-macro.S point at the same data.
55*4882a593Smuzhiyun */
56*4882a593Smuzhiyun u32 tegra_uart_config[3] = {
57*4882a593Smuzhiyun /* Debug UART initialization required */
58*4882a593Smuzhiyun 1,
59*4882a593Smuzhiyun /* Debug UART physical address */
60*4882a593Smuzhiyun 0,
61*4882a593Smuzhiyun /* Debug UART virtual address */
62*4882a593Smuzhiyun 0,
63*4882a593Smuzhiyun };
64*4882a593Smuzhiyun
tegra_init_early(void)65*4882a593Smuzhiyun static void __init tegra_init_early(void)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun of_register_trusted_foundations();
68*4882a593Smuzhiyun tegra_cpu_reset_handler_init();
69*4882a593Smuzhiyun call_firmware_op(l2x0_init);
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
tegra_dt_init_irq(void)72*4882a593Smuzhiyun static void __init tegra_dt_init_irq(void)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun tegra_init_irq();
75*4882a593Smuzhiyun irqchip_init();
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
tegra_dt_init(void)78*4882a593Smuzhiyun static void __init tegra_dt_init(void)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun struct device *parent = tegra_soc_device_register();
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun of_platform_default_populate(NULL, NULL, parent);
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
tegra_dt_init_late(void)85*4882a593Smuzhiyun static void __init tegra_dt_init_late(void)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun tegra_init_suspend();
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) &&
90*4882a593Smuzhiyun of_machine_is_compatible("compal,paz00"))
91*4882a593Smuzhiyun tegra_paz00_wifikill_init();
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) &&
94*4882a593Smuzhiyun of_machine_is_compatible("nvidia,tegra20"))
95*4882a593Smuzhiyun platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0);
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun if (IS_ENABLED(CONFIG_ARM_TEGRA_CPUIDLE) && !psci_smp_available())
98*4882a593Smuzhiyun platform_device_register_simple("tegra-cpuidle", -1, NULL, 0);
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) &&
101*4882a593Smuzhiyun of_machine_is_compatible("nvidia,tegra30"))
102*4882a593Smuzhiyun platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0);
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun static const char * const tegra_dt_board_compat[] = {
106*4882a593Smuzhiyun "nvidia,tegra124",
107*4882a593Smuzhiyun "nvidia,tegra114",
108*4882a593Smuzhiyun "nvidia,tegra30",
109*4882a593Smuzhiyun "nvidia,tegra20",
110*4882a593Smuzhiyun NULL
111*4882a593Smuzhiyun };
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun DT_MACHINE_START(TEGRA_DT, "NVIDIA Tegra SoC (Flattened Device Tree)")
114*4882a593Smuzhiyun .l2c_aux_val = 0x3c400000,
115*4882a593Smuzhiyun .l2c_aux_mask = 0xc20fc3ff,
116*4882a593Smuzhiyun .smp = smp_ops(tegra_smp_ops),
117*4882a593Smuzhiyun .map_io = tegra_map_common_io,
118*4882a593Smuzhiyun .init_early = tegra_init_early,
119*4882a593Smuzhiyun .init_irq = tegra_dt_init_irq,
120*4882a593Smuzhiyun .init_machine = tegra_dt_init,
121*4882a593Smuzhiyun .init_late = tegra_dt_init_late,
122*4882a593Smuzhiyun .dt_compat = tegra_dt_board_compat,
123*4882a593Smuzhiyun MACHINE_END
124