1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * arch/arm/mach-tegra/reset.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * CPU reset dispatcher. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Copyright (c) 2011, NVIDIA Corporation. 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __MACH_TEGRA_RESET_H 11*4882a593Smuzhiyun #define __MACH_TEGRA_RESET_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define TEGRA_RESET_MASK_PRESENT 0 14*4882a593Smuzhiyun #define TEGRA_RESET_MASK_LP1 1 15*4882a593Smuzhiyun #define TEGRA_RESET_MASK_LP2 2 16*4882a593Smuzhiyun #define TEGRA_RESET_STARTUP_SECONDARY 3 17*4882a593Smuzhiyun #define TEGRA_RESET_STARTUP_LP2 4 18*4882a593Smuzhiyun #define TEGRA_RESET_STARTUP_LP1 5 19*4882a593Smuzhiyun #define TEGRA_RESET_TF_PRESENT 6 20*4882a593Smuzhiyun #define TEGRA_RESET_DATA_SIZE 7 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define RESET_DATA(x) ((TEGRA_RESET_##x)*4) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #include "irammap.h" 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun extern unsigned long __tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE]; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun void __tegra_cpu_reset_handler_start(void); 31*4882a593Smuzhiyun void __tegra_cpu_reset_handler(void); 32*4882a593Smuzhiyun void __tegra20_cpu1_resettable_status_offset(void); 33*4882a593Smuzhiyun void __tegra_cpu_reset_handler_end(void); 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP 36*4882a593Smuzhiyun #define tegra_cpu_lp1_mask \ 37*4882a593Smuzhiyun (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \ 38*4882a593Smuzhiyun ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP1] - \ 39*4882a593Smuzhiyun (u32)__tegra_cpu_reset_handler_start))) 40*4882a593Smuzhiyun #define tegra_cpu_lp2_mask \ 41*4882a593Smuzhiyun (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \ 42*4882a593Smuzhiyun ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP2] - \ 43*4882a593Smuzhiyun (u32)__tegra_cpu_reset_handler_start))) 44*4882a593Smuzhiyun #endif 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define tegra_cpu_reset_handler_offset \ 47*4882a593Smuzhiyun ((u32)__tegra_cpu_reset_handler - \ 48*4882a593Smuzhiyun (u32)__tegra_cpu_reset_handler_start) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define tegra_cpu_reset_handler_size \ 51*4882a593Smuzhiyun (__tegra_cpu_reset_handler_end - \ 52*4882a593Smuzhiyun __tegra_cpu_reset_handler_start) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun void __init tegra_cpu_reset_handler_init(void); 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #endif 57*4882a593Smuzhiyun #endif 58