1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __MACH_TEGRA_IRAMMAP_H 7*4882a593Smuzhiyun #define __MACH_TEGRA_IRAMMAP_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/sizes.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* The first 1K of IRAM is permanently reserved for the CPU reset handler */ 12*4882a593Smuzhiyun #define TEGRA_IRAM_RESET_HANDLER_OFFSET 0 13*4882a593Smuzhiyun #define TEGRA_IRAM_RESET_HANDLER_SIZE SZ_1K 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* 16*4882a593Smuzhiyun * This area is used for LPx resume vector, only while LPx power state is 17*4882a593Smuzhiyun * active. At other times, the AVP may use this area for arbitrary purposes 18*4882a593Smuzhiyun */ 19*4882a593Smuzhiyun #define TEGRA_IRAM_LPx_RESUME_AREA (TEGRA_IRAM_BASE + SZ_4K) 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #endif 22