1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2010 Google, Inc. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author: 6*4882a593Smuzhiyun * Colin Cross <ccross@google.com> 7*4882a593Smuzhiyun * Erik Gilling <konkers@google.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __MACH_TEGRA_IOMAP_H 11*4882a593Smuzhiyun #define __MACH_TEGRA_IOMAP_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <linux/pgtable.h> 14*4882a593Smuzhiyun #include <linux/sizes.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define TEGRA_IRAM_BASE 0x40000000 17*4882a593Smuzhiyun #define TEGRA_IRAM_SIZE SZ_256K 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define TEGRA_ARM_PERIF_BASE 0x50040000 20*4882a593Smuzhiyun #define TEGRA_ARM_PERIF_SIZE SZ_8K 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define TEGRA_ARM_INT_DIST_BASE 0x50041000 23*4882a593Smuzhiyun #define TEGRA_ARM_INT_DIST_SIZE SZ_4K 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define TEGRA_TMR1_BASE 0x60005000 26*4882a593Smuzhiyun #define TEGRA_TMR1_SIZE SZ_8 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define TEGRA_TMR2_BASE 0x60005008 29*4882a593Smuzhiyun #define TEGRA_TMR2_SIZE SZ_8 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define TEGRA_TMRUS_BASE 0x60005010 32*4882a593Smuzhiyun #define TEGRA_TMRUS_SIZE SZ_64 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define TEGRA_TMR3_BASE 0x60005050 35*4882a593Smuzhiyun #define TEGRA_TMR3_SIZE SZ_8 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define TEGRA_TMR4_BASE 0x60005058 38*4882a593Smuzhiyun #define TEGRA_TMR4_SIZE SZ_8 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define TEGRA_CLK_RESET_BASE 0x60006000 41*4882a593Smuzhiyun #define TEGRA_CLK_RESET_SIZE SZ_4K 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define TEGRA_FLOW_CTRL_BASE 0x60007000 44*4882a593Smuzhiyun #define TEGRA_FLOW_CTRL_SIZE 20 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define TEGRA_SB_BASE 0x6000C200 47*4882a593Smuzhiyun #define TEGRA_SB_SIZE 256 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define TEGRA_EXCEPTION_VECTORS_BASE 0x6000F000 50*4882a593Smuzhiyun #define TEGRA_EXCEPTION_VECTORS_SIZE SZ_4K 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define TEGRA_APB_MISC_BASE 0x70000000 53*4882a593Smuzhiyun #define TEGRA_APB_MISC_SIZE SZ_4K 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define TEGRA_UARTA_BASE 0x70006000 56*4882a593Smuzhiyun #define TEGRA_UARTA_SIZE SZ_64 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define TEGRA_UARTB_BASE 0x70006040 59*4882a593Smuzhiyun #define TEGRA_UARTB_SIZE SZ_64 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define TEGRA_UARTC_BASE 0x70006200 62*4882a593Smuzhiyun #define TEGRA_UARTC_SIZE SZ_256 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define TEGRA_UARTD_BASE 0x70006300 65*4882a593Smuzhiyun #define TEGRA_UARTD_SIZE SZ_256 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define TEGRA_UARTE_BASE 0x70006400 68*4882a593Smuzhiyun #define TEGRA_UARTE_SIZE SZ_256 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define TEGRA_PMC_BASE 0x7000E400 71*4882a593Smuzhiyun #define TEGRA_PMC_SIZE SZ_256 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define TEGRA_EMC_BASE 0x7000F400 74*4882a593Smuzhiyun #define TEGRA_EMC_SIZE SZ_1K 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define TEGRA_EMC0_BASE 0x7001A000 77*4882a593Smuzhiyun #define TEGRA_EMC0_SIZE SZ_2K 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #define TEGRA_EMC1_BASE 0x7001A800 80*4882a593Smuzhiyun #define TEGRA_EMC1_SIZE SZ_2K 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define TEGRA124_EMC_BASE 0x7001B000 83*4882a593Smuzhiyun #define TEGRA124_EMC_SIZE SZ_2K 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define TEGRA_CSITE_BASE 0x70040000 86*4882a593Smuzhiyun #define TEGRA_CSITE_SIZE SZ_256K 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* On TEGRA, many peripherals are very closely packed in 89*4882a593Smuzhiyun * two 256MB io windows (that actually only use about 64KB 90*4882a593Smuzhiyun * at the start of each). 91*4882a593Smuzhiyun * 92*4882a593Smuzhiyun * We will just map the first MMU section of each window (to minimize 93*4882a593Smuzhiyun * pt entries needed) and provide a macro to transform physical 94*4882a593Smuzhiyun * io addresses to an appropriate void __iomem *. 95*4882a593Smuzhiyun */ 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define IO_IRAM_PHYS 0x40000000 98*4882a593Smuzhiyun #define IO_IRAM_VIRT IOMEM(0xFE400000) 99*4882a593Smuzhiyun #define IO_IRAM_SIZE SZ_256K 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #define IO_CPU_PHYS 0x50040000 102*4882a593Smuzhiyun #define IO_CPU_VIRT IOMEM(0xFE440000) 103*4882a593Smuzhiyun #define IO_CPU_SIZE SZ_16K 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #define IO_PPSB_PHYS 0x60000000 106*4882a593Smuzhiyun #define IO_PPSB_VIRT IOMEM(0xFE200000) 107*4882a593Smuzhiyun #define IO_PPSB_SIZE SECTION_SIZE 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun #define IO_APB_PHYS 0x70000000 110*4882a593Smuzhiyun #define IO_APB_VIRT IOMEM(0xFE000000) 111*4882a593Smuzhiyun #define IO_APB_SIZE SECTION_SIZE 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #define IO_TO_VIRT_BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz))) 114*4882a593Smuzhiyun #define IO_TO_VIRT_XLATE(p, pst, vst) (((p) - (pst) + (vst))) 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun #define IO_TO_VIRT(n) ( \ 117*4882a593Smuzhiyun IO_TO_VIRT_BETWEEN((n), IO_PPSB_PHYS, IO_PPSB_SIZE) ? \ 118*4882a593Smuzhiyun IO_TO_VIRT_XLATE((n), IO_PPSB_PHYS, IO_PPSB_VIRT) : \ 119*4882a593Smuzhiyun IO_TO_VIRT_BETWEEN((n), IO_APB_PHYS, IO_APB_SIZE) ? \ 120*4882a593Smuzhiyun IO_TO_VIRT_XLATE((n), IO_APB_PHYS, IO_APB_VIRT) : \ 121*4882a593Smuzhiyun IO_TO_VIRT_BETWEEN((n), IO_CPU_PHYS, IO_CPU_SIZE) ? \ 122*4882a593Smuzhiyun IO_TO_VIRT_XLATE((n), IO_CPU_PHYS, IO_CPU_VIRT) : \ 123*4882a593Smuzhiyun IO_TO_VIRT_BETWEEN((n), IO_IRAM_PHYS, IO_IRAM_SIZE) ? \ 124*4882a593Smuzhiyun IO_TO_VIRT_XLATE((n), IO_IRAM_PHYS, IO_IRAM_VIRT) : \ 125*4882a593Smuzhiyun NULL) 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun #define IO_ADDRESS(n) (IO_TO_VIRT(n)) 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun #endif 130