1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * arch/arm/mach-spear3xx/spear3xx.c
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPEAr3XX machines common source file
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 2009-2012 ST Microelectronics
7*4882a593Smuzhiyun * Viresh Kumar <vireshk@kernel.org>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public
10*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any
11*4882a593Smuzhiyun * warranty of any kind, whether express or implied.
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #define pr_fmt(fmt) "SPEAr3xx: " fmt
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include <linux/amba/pl022.h>
17*4882a593Smuzhiyun #include <linux/amba/pl080.h>
18*4882a593Smuzhiyun #include <linux/clk.h>
19*4882a593Smuzhiyun #include <linux/io.h>
20*4882a593Smuzhiyun #include <asm/mach/map.h>
21*4882a593Smuzhiyun #include "pl080.h"
22*4882a593Smuzhiyun #include "generic.h"
23*4882a593Smuzhiyun #include <mach/spear.h>
24*4882a593Smuzhiyun #include <mach/misc_regs.h>
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* ssp device registration */
27*4882a593Smuzhiyun struct pl022_ssp_controller pl022_plat_data = {
28*4882a593Smuzhiyun .bus_id = 0,
29*4882a593Smuzhiyun .enable_dma = 1,
30*4882a593Smuzhiyun .dma_filter = pl08x_filter_id,
31*4882a593Smuzhiyun .dma_tx_param = "ssp0_tx",
32*4882a593Smuzhiyun .dma_rx_param = "ssp0_rx",
33*4882a593Smuzhiyun /*
34*4882a593Smuzhiyun * This is number of spi devices that can be connected to spi. There are
35*4882a593Smuzhiyun * two type of chipselects on which slave devices can work. One is chip
36*4882a593Smuzhiyun * select provided by spi masters other is controlled through external
37*4882a593Smuzhiyun * gpio's. We can't use chipselect provided from spi master (because as
38*4882a593Smuzhiyun * soon as FIFO becomes empty, CS is disabled and transfer ends). So
39*4882a593Smuzhiyun * this number now depends on number of gpios available for spi. each
40*4882a593Smuzhiyun * slave on each master requires a separate gpio pin.
41*4882a593Smuzhiyun */
42*4882a593Smuzhiyun .num_chipselect = 2,
43*4882a593Smuzhiyun };
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun /* dmac device registration */
46*4882a593Smuzhiyun struct pl08x_platform_data pl080_plat_data = {
47*4882a593Smuzhiyun .memcpy_burst_size = PL08X_BURST_SZ_16,
48*4882a593Smuzhiyun .memcpy_bus_width = PL08X_BUS_WIDTH_32_BITS,
49*4882a593Smuzhiyun .memcpy_prot_buff = true,
50*4882a593Smuzhiyun .memcpy_prot_cache = true,
51*4882a593Smuzhiyun .lli_buses = PL08X_AHB1,
52*4882a593Smuzhiyun .mem_buses = PL08X_AHB1,
53*4882a593Smuzhiyun .get_xfer_signal = pl080_get_signal,
54*4882a593Smuzhiyun .put_xfer_signal = pl080_put_signal,
55*4882a593Smuzhiyun };
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun /*
58*4882a593Smuzhiyun * Following will create 16MB static virtual/physical mappings
59*4882a593Smuzhiyun * PHYSICAL VIRTUAL
60*4882a593Smuzhiyun * 0xD0000000 0xFD000000
61*4882a593Smuzhiyun * 0xFC000000 0xFC000000
62*4882a593Smuzhiyun */
63*4882a593Smuzhiyun struct map_desc spear3xx_io_desc[] __initdata = {
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun .virtual = (unsigned long)VA_SPEAR_ICM1_2_BASE,
66*4882a593Smuzhiyun .pfn = __phys_to_pfn(SPEAR_ICM1_2_BASE),
67*4882a593Smuzhiyun .length = SZ_16M,
68*4882a593Smuzhiyun .type = MT_DEVICE
69*4882a593Smuzhiyun }, {
70*4882a593Smuzhiyun .virtual = (unsigned long)VA_SPEAR_ICM3_SMI_CTRL_BASE,
71*4882a593Smuzhiyun .pfn = __phys_to_pfn(SPEAR_ICM3_SMI_CTRL_BASE),
72*4882a593Smuzhiyun .length = SZ_16M,
73*4882a593Smuzhiyun .type = MT_DEVICE
74*4882a593Smuzhiyun },
75*4882a593Smuzhiyun };
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun /* This will create static memory mapping for selected devices */
spear3xx_map_io(void)78*4882a593Smuzhiyun void __init spear3xx_map_io(void)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc));
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
spear3xx_timer_init(void)83*4882a593Smuzhiyun void __init spear3xx_timer_init(void)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun char pclk_name[] = "pll3_clk";
86*4882a593Smuzhiyun struct clk *gpt_clk, *pclk;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun spear3xx_clk_init(MISC_BASE, VA_SPEAR320_SOC_CONFIG_BASE);
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun /* get the system timer clock */
91*4882a593Smuzhiyun gpt_clk = clk_get_sys("gpt0", NULL);
92*4882a593Smuzhiyun if (IS_ERR(gpt_clk)) {
93*4882a593Smuzhiyun pr_err("%s:couldn't get clk for gpt\n", __func__);
94*4882a593Smuzhiyun BUG();
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun /* get the suitable parent clock for timer*/
98*4882a593Smuzhiyun pclk = clk_get(NULL, pclk_name);
99*4882a593Smuzhiyun if (IS_ERR(pclk)) {
100*4882a593Smuzhiyun pr_err("%s:couldn't get %s as parent for gpt\n",
101*4882a593Smuzhiyun __func__, pclk_name);
102*4882a593Smuzhiyun BUG();
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun clk_set_parent(gpt_clk, pclk);
106*4882a593Smuzhiyun clk_put(gpt_clk);
107*4882a593Smuzhiyun clk_put(pclk);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun spear_setup_of_timer();
110*4882a593Smuzhiyun }
111