1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * arch/arm/mach-spear3xx/spear310.c
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPEAr310 machine source file
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 2009-2012 ST Microelectronics
7*4882a593Smuzhiyun * Viresh Kumar <vireshk@kernel.org>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public
10*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any
11*4882a593Smuzhiyun * warranty of any kind, whether express or implied.
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #define pr_fmt(fmt) "SPEAr310: " fmt
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include <linux/amba/pl08x.h>
17*4882a593Smuzhiyun #include <linux/amba/serial.h>
18*4882a593Smuzhiyun #include <linux/of_platform.h>
19*4882a593Smuzhiyun #include <asm/mach/arch.h>
20*4882a593Smuzhiyun #include "generic.h"
21*4882a593Smuzhiyun #include <mach/spear.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define SPEAR310_UART1_BASE UL(0xB2000000)
24*4882a593Smuzhiyun #define SPEAR310_UART2_BASE UL(0xB2080000)
25*4882a593Smuzhiyun #define SPEAR310_UART3_BASE UL(0xB2100000)
26*4882a593Smuzhiyun #define SPEAR310_UART4_BASE UL(0xB2180000)
27*4882a593Smuzhiyun #define SPEAR310_UART5_BASE UL(0xB2200000)
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /* DMAC platform data's slave info */
30*4882a593Smuzhiyun struct pl08x_channel_data spear310_dma_info[] = {
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun .bus_id = "uart0_rx",
33*4882a593Smuzhiyun .min_signal = 2,
34*4882a593Smuzhiyun .max_signal = 2,
35*4882a593Smuzhiyun .muxval = 0,
36*4882a593Smuzhiyun .periph_buses = PL08X_AHB1,
37*4882a593Smuzhiyun }, {
38*4882a593Smuzhiyun .bus_id = "uart0_tx",
39*4882a593Smuzhiyun .min_signal = 3,
40*4882a593Smuzhiyun .max_signal = 3,
41*4882a593Smuzhiyun .muxval = 0,
42*4882a593Smuzhiyun .periph_buses = PL08X_AHB1,
43*4882a593Smuzhiyun }, {
44*4882a593Smuzhiyun .bus_id = "ssp0_rx",
45*4882a593Smuzhiyun .min_signal = 8,
46*4882a593Smuzhiyun .max_signal = 8,
47*4882a593Smuzhiyun .muxval = 0,
48*4882a593Smuzhiyun .periph_buses = PL08X_AHB1,
49*4882a593Smuzhiyun }, {
50*4882a593Smuzhiyun .bus_id = "ssp0_tx",
51*4882a593Smuzhiyun .min_signal = 9,
52*4882a593Smuzhiyun .max_signal = 9,
53*4882a593Smuzhiyun .muxval = 0,
54*4882a593Smuzhiyun .periph_buses = PL08X_AHB1,
55*4882a593Smuzhiyun }, {
56*4882a593Smuzhiyun .bus_id = "i2c_rx",
57*4882a593Smuzhiyun .min_signal = 10,
58*4882a593Smuzhiyun .max_signal = 10,
59*4882a593Smuzhiyun .muxval = 0,
60*4882a593Smuzhiyun .periph_buses = PL08X_AHB1,
61*4882a593Smuzhiyun }, {
62*4882a593Smuzhiyun .bus_id = "i2c_tx",
63*4882a593Smuzhiyun .min_signal = 11,
64*4882a593Smuzhiyun .max_signal = 11,
65*4882a593Smuzhiyun .muxval = 0,
66*4882a593Smuzhiyun .periph_buses = PL08X_AHB1,
67*4882a593Smuzhiyun }, {
68*4882a593Smuzhiyun .bus_id = "irda",
69*4882a593Smuzhiyun .min_signal = 12,
70*4882a593Smuzhiyun .max_signal = 12,
71*4882a593Smuzhiyun .muxval = 0,
72*4882a593Smuzhiyun .periph_buses = PL08X_AHB1,
73*4882a593Smuzhiyun }, {
74*4882a593Smuzhiyun .bus_id = "adc",
75*4882a593Smuzhiyun .min_signal = 13,
76*4882a593Smuzhiyun .max_signal = 13,
77*4882a593Smuzhiyun .muxval = 0,
78*4882a593Smuzhiyun .periph_buses = PL08X_AHB1,
79*4882a593Smuzhiyun }, {
80*4882a593Smuzhiyun .bus_id = "to_jpeg",
81*4882a593Smuzhiyun .min_signal = 14,
82*4882a593Smuzhiyun .max_signal = 14,
83*4882a593Smuzhiyun .muxval = 0,
84*4882a593Smuzhiyun .periph_buses = PL08X_AHB1,
85*4882a593Smuzhiyun }, {
86*4882a593Smuzhiyun .bus_id = "from_jpeg",
87*4882a593Smuzhiyun .min_signal = 15,
88*4882a593Smuzhiyun .max_signal = 15,
89*4882a593Smuzhiyun .muxval = 0,
90*4882a593Smuzhiyun .periph_buses = PL08X_AHB1,
91*4882a593Smuzhiyun }, {
92*4882a593Smuzhiyun .bus_id = "uart1_rx",
93*4882a593Smuzhiyun .min_signal = 0,
94*4882a593Smuzhiyun .max_signal = 0,
95*4882a593Smuzhiyun .muxval = 1,
96*4882a593Smuzhiyun .periph_buses = PL08X_AHB1,
97*4882a593Smuzhiyun }, {
98*4882a593Smuzhiyun .bus_id = "uart1_tx",
99*4882a593Smuzhiyun .min_signal = 1,
100*4882a593Smuzhiyun .max_signal = 1,
101*4882a593Smuzhiyun .muxval = 1,
102*4882a593Smuzhiyun .periph_buses = PL08X_AHB1,
103*4882a593Smuzhiyun }, {
104*4882a593Smuzhiyun .bus_id = "uart2_rx",
105*4882a593Smuzhiyun .min_signal = 2,
106*4882a593Smuzhiyun .max_signal = 2,
107*4882a593Smuzhiyun .muxval = 1,
108*4882a593Smuzhiyun .periph_buses = PL08X_AHB1,
109*4882a593Smuzhiyun }, {
110*4882a593Smuzhiyun .bus_id = "uart2_tx",
111*4882a593Smuzhiyun .min_signal = 3,
112*4882a593Smuzhiyun .max_signal = 3,
113*4882a593Smuzhiyun .muxval = 1,
114*4882a593Smuzhiyun .periph_buses = PL08X_AHB1,
115*4882a593Smuzhiyun }, {
116*4882a593Smuzhiyun .bus_id = "uart3_rx",
117*4882a593Smuzhiyun .min_signal = 4,
118*4882a593Smuzhiyun .max_signal = 4,
119*4882a593Smuzhiyun .muxval = 1,
120*4882a593Smuzhiyun .periph_buses = PL08X_AHB1,
121*4882a593Smuzhiyun }, {
122*4882a593Smuzhiyun .bus_id = "uart3_tx",
123*4882a593Smuzhiyun .min_signal = 5,
124*4882a593Smuzhiyun .max_signal = 5,
125*4882a593Smuzhiyun .muxval = 1,
126*4882a593Smuzhiyun .periph_buses = PL08X_AHB1,
127*4882a593Smuzhiyun }, {
128*4882a593Smuzhiyun .bus_id = "uart4_rx",
129*4882a593Smuzhiyun .min_signal = 6,
130*4882a593Smuzhiyun .max_signal = 6,
131*4882a593Smuzhiyun .muxval = 1,
132*4882a593Smuzhiyun .periph_buses = PL08X_AHB1,
133*4882a593Smuzhiyun }, {
134*4882a593Smuzhiyun .bus_id = "uart4_tx",
135*4882a593Smuzhiyun .min_signal = 7,
136*4882a593Smuzhiyun .max_signal = 7,
137*4882a593Smuzhiyun .muxval = 1,
138*4882a593Smuzhiyun .periph_buses = PL08X_AHB1,
139*4882a593Smuzhiyun }, {
140*4882a593Smuzhiyun .bus_id = "uart5_rx",
141*4882a593Smuzhiyun .min_signal = 8,
142*4882a593Smuzhiyun .max_signal = 8,
143*4882a593Smuzhiyun .muxval = 1,
144*4882a593Smuzhiyun .periph_buses = PL08X_AHB1,
145*4882a593Smuzhiyun }, {
146*4882a593Smuzhiyun .bus_id = "uart5_tx",
147*4882a593Smuzhiyun .min_signal = 9,
148*4882a593Smuzhiyun .max_signal = 9,
149*4882a593Smuzhiyun .muxval = 1,
150*4882a593Smuzhiyun .periph_buses = PL08X_AHB1,
151*4882a593Smuzhiyun }, {
152*4882a593Smuzhiyun .bus_id = "ras5_rx",
153*4882a593Smuzhiyun .min_signal = 10,
154*4882a593Smuzhiyun .max_signal = 10,
155*4882a593Smuzhiyun .muxval = 1,
156*4882a593Smuzhiyun .periph_buses = PL08X_AHB1,
157*4882a593Smuzhiyun }, {
158*4882a593Smuzhiyun .bus_id = "ras5_tx",
159*4882a593Smuzhiyun .min_signal = 11,
160*4882a593Smuzhiyun .max_signal = 11,
161*4882a593Smuzhiyun .muxval = 1,
162*4882a593Smuzhiyun .periph_buses = PL08X_AHB1,
163*4882a593Smuzhiyun }, {
164*4882a593Smuzhiyun .bus_id = "ras6_rx",
165*4882a593Smuzhiyun .min_signal = 12,
166*4882a593Smuzhiyun .max_signal = 12,
167*4882a593Smuzhiyun .muxval = 1,
168*4882a593Smuzhiyun .periph_buses = PL08X_AHB1,
169*4882a593Smuzhiyun }, {
170*4882a593Smuzhiyun .bus_id = "ras6_tx",
171*4882a593Smuzhiyun .min_signal = 13,
172*4882a593Smuzhiyun .max_signal = 13,
173*4882a593Smuzhiyun .muxval = 1,
174*4882a593Smuzhiyun .periph_buses = PL08X_AHB1,
175*4882a593Smuzhiyun }, {
176*4882a593Smuzhiyun .bus_id = "ras7_rx",
177*4882a593Smuzhiyun .min_signal = 14,
178*4882a593Smuzhiyun .max_signal = 14,
179*4882a593Smuzhiyun .muxval = 1,
180*4882a593Smuzhiyun .periph_buses = PL08X_AHB1,
181*4882a593Smuzhiyun }, {
182*4882a593Smuzhiyun .bus_id = "ras7_tx",
183*4882a593Smuzhiyun .min_signal = 15,
184*4882a593Smuzhiyun .max_signal = 15,
185*4882a593Smuzhiyun .muxval = 1,
186*4882a593Smuzhiyun .periph_buses = PL08X_AHB1,
187*4882a593Smuzhiyun },
188*4882a593Smuzhiyun };
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun /* uart devices plat data */
191*4882a593Smuzhiyun static struct amba_pl011_data spear310_uart_data[] = {
192*4882a593Smuzhiyun {
193*4882a593Smuzhiyun .dma_filter = pl08x_filter_id,
194*4882a593Smuzhiyun .dma_tx_param = "uart1_tx",
195*4882a593Smuzhiyun .dma_rx_param = "uart1_rx",
196*4882a593Smuzhiyun }, {
197*4882a593Smuzhiyun .dma_filter = pl08x_filter_id,
198*4882a593Smuzhiyun .dma_tx_param = "uart2_tx",
199*4882a593Smuzhiyun .dma_rx_param = "uart2_rx",
200*4882a593Smuzhiyun }, {
201*4882a593Smuzhiyun .dma_filter = pl08x_filter_id,
202*4882a593Smuzhiyun .dma_tx_param = "uart3_tx",
203*4882a593Smuzhiyun .dma_rx_param = "uart3_rx",
204*4882a593Smuzhiyun }, {
205*4882a593Smuzhiyun .dma_filter = pl08x_filter_id,
206*4882a593Smuzhiyun .dma_tx_param = "uart4_tx",
207*4882a593Smuzhiyun .dma_rx_param = "uart4_rx",
208*4882a593Smuzhiyun }, {
209*4882a593Smuzhiyun .dma_filter = pl08x_filter_id,
210*4882a593Smuzhiyun .dma_tx_param = "uart5_tx",
211*4882a593Smuzhiyun .dma_rx_param = "uart5_rx",
212*4882a593Smuzhiyun },
213*4882a593Smuzhiyun };
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun /* Add SPEAr310 auxdata to pass platform data */
216*4882a593Smuzhiyun static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = {
217*4882a593Smuzhiyun OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
218*4882a593Smuzhiyun &pl022_plat_data),
219*4882a593Smuzhiyun OF_DEV_AUXDATA("arm,pl080", SPEAR_ICM3_DMA_BASE, NULL,
220*4882a593Smuzhiyun &pl080_plat_data),
221*4882a593Smuzhiyun OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART1_BASE, NULL,
222*4882a593Smuzhiyun &spear310_uart_data[0]),
223*4882a593Smuzhiyun OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART2_BASE, NULL,
224*4882a593Smuzhiyun &spear310_uart_data[1]),
225*4882a593Smuzhiyun OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART3_BASE, NULL,
226*4882a593Smuzhiyun &spear310_uart_data[2]),
227*4882a593Smuzhiyun OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART4_BASE, NULL,
228*4882a593Smuzhiyun &spear310_uart_data[3]),
229*4882a593Smuzhiyun OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART5_BASE, NULL,
230*4882a593Smuzhiyun &spear310_uart_data[4]),
231*4882a593Smuzhiyun {}
232*4882a593Smuzhiyun };
233*4882a593Smuzhiyun
spear310_dt_init(void)234*4882a593Smuzhiyun static void __init spear310_dt_init(void)
235*4882a593Smuzhiyun {
236*4882a593Smuzhiyun pl080_plat_data.slave_channels = spear310_dma_info;
237*4882a593Smuzhiyun pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info);
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun of_platform_default_populate(NULL, spear310_auxdata_lookup, NULL);
240*4882a593Smuzhiyun }
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun static const char * const spear310_dt_board_compat[] = {
243*4882a593Smuzhiyun "st,spear310",
244*4882a593Smuzhiyun "st,spear310-evb",
245*4882a593Smuzhiyun NULL,
246*4882a593Smuzhiyun };
247*4882a593Smuzhiyun
spear310_map_io(void)248*4882a593Smuzhiyun static void __init spear310_map_io(void)
249*4882a593Smuzhiyun {
250*4882a593Smuzhiyun spear3xx_map_io();
251*4882a593Smuzhiyun }
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree")
254*4882a593Smuzhiyun .map_io = spear310_map_io,
255*4882a593Smuzhiyun .init_time = spear3xx_timer_init,
256*4882a593Smuzhiyun .init_machine = spear310_dt_init,
257*4882a593Smuzhiyun .restart = spear_restart,
258*4882a593Smuzhiyun .dt_compat = spear310_dt_board_compat,
259*4882a593Smuzhiyun MACHINE_END
260