1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * arch/arm/mach-spear13xx/spear13xx.c
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPEAr13XX machines common source file
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 2012 ST Microelectronics
7*4882a593Smuzhiyun * Viresh Kumar <vireshk@kernel.org>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public
10*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any
11*4882a593Smuzhiyun * warranty of any kind, whether express or implied.
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #define pr_fmt(fmt) "SPEAr13xx: " fmt
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include <linux/amba/pl022.h>
17*4882a593Smuzhiyun #include <linux/clk.h>
18*4882a593Smuzhiyun #include <linux/clocksource.h>
19*4882a593Smuzhiyun #include <linux/err.h>
20*4882a593Smuzhiyun #include <linux/of.h>
21*4882a593Smuzhiyun #include <asm/hardware/cache-l2x0.h>
22*4882a593Smuzhiyun #include <asm/mach/map.h>
23*4882a593Smuzhiyun #include <mach/spear.h>
24*4882a593Smuzhiyun #include "generic.h"
25*4882a593Smuzhiyun
spear13xx_l2x0_init(void)26*4882a593Smuzhiyun void __init spear13xx_l2x0_init(void)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun /*
29*4882a593Smuzhiyun * 512KB (64KB/way), 8-way associativity, parity supported
30*4882a593Smuzhiyun *
31*4882a593Smuzhiyun * FIXME: 9th bit, of Auxillary Controller register must be set
32*4882a593Smuzhiyun * for some spear13xx devices for stable L2 operation.
33*4882a593Smuzhiyun *
34*4882a593Smuzhiyun * Enable Early BRESP, L2 prefetch for Instruction and Data,
35*4882a593Smuzhiyun * write alloc and 'Full line of zero' options
36*4882a593Smuzhiyun *
37*4882a593Smuzhiyun */
38*4882a593Smuzhiyun if (!IS_ENABLED(CONFIG_CACHE_L2X0))
39*4882a593Smuzhiyun return;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun writel_relaxed(0x06, VA_L2CC_BASE + L310_PREFETCH_CTRL);
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun /*
44*4882a593Smuzhiyun * Program following latencies in order to make
45*4882a593Smuzhiyun * SPEAr1340 work at 600 MHz
46*4882a593Smuzhiyun */
47*4882a593Smuzhiyun writel_relaxed(0x221, VA_L2CC_BASE + L310_TAG_LATENCY_CTRL);
48*4882a593Smuzhiyun writel_relaxed(0x441, VA_L2CC_BASE + L310_DATA_LATENCY_CTRL);
49*4882a593Smuzhiyun l2x0_init(VA_L2CC_BASE, 0x30a00001, 0xfe0fffff);
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /*
53*4882a593Smuzhiyun * Following will create 16MB static virtual/physical mappings
54*4882a593Smuzhiyun * PHYSICAL VIRTUAL
55*4882a593Smuzhiyun * 0xB3000000 0xF9000000
56*4882a593Smuzhiyun * 0xE0000000 0xFD000000
57*4882a593Smuzhiyun * 0xEC000000 0xFC000000
58*4882a593Smuzhiyun * 0xED000000 0xFB000000
59*4882a593Smuzhiyun */
60*4882a593Smuzhiyun static struct map_desc spear13xx_io_desc[] __initdata = {
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun .virtual = (unsigned long)VA_PERIP_GRP2_BASE,
63*4882a593Smuzhiyun .pfn = __phys_to_pfn(PERIP_GRP2_BASE),
64*4882a593Smuzhiyun .length = SZ_16M,
65*4882a593Smuzhiyun .type = MT_DEVICE
66*4882a593Smuzhiyun }, {
67*4882a593Smuzhiyun .virtual = (unsigned long)VA_PERIP_GRP1_BASE,
68*4882a593Smuzhiyun .pfn = __phys_to_pfn(PERIP_GRP1_BASE),
69*4882a593Smuzhiyun .length = SZ_16M,
70*4882a593Smuzhiyun .type = MT_DEVICE
71*4882a593Smuzhiyun }, {
72*4882a593Smuzhiyun .virtual = (unsigned long)VA_A9SM_AND_MPMC_BASE,
73*4882a593Smuzhiyun .pfn = __phys_to_pfn(A9SM_AND_MPMC_BASE),
74*4882a593Smuzhiyun .length = SZ_16M,
75*4882a593Smuzhiyun .type = MT_DEVICE
76*4882a593Smuzhiyun }, {
77*4882a593Smuzhiyun .virtual = (unsigned long)VA_L2CC_BASE,
78*4882a593Smuzhiyun .pfn = __phys_to_pfn(L2CC_BASE),
79*4882a593Smuzhiyun .length = SZ_4K,
80*4882a593Smuzhiyun .type = MT_DEVICE
81*4882a593Smuzhiyun },
82*4882a593Smuzhiyun };
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /* This will create static memory mapping for selected devices */
spear13xx_map_io(void)85*4882a593Smuzhiyun void __init spear13xx_map_io(void)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun iotable_init(spear13xx_io_desc, ARRAY_SIZE(spear13xx_io_desc));
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
spear13xx_clk_init(void)90*4882a593Smuzhiyun static void __init spear13xx_clk_init(void)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun if (of_machine_is_compatible("st,spear1310"))
93*4882a593Smuzhiyun spear1310_clk_init(VA_MISC_BASE, VA_SPEAR1310_RAS_BASE);
94*4882a593Smuzhiyun else if (of_machine_is_compatible("st,spear1340"))
95*4882a593Smuzhiyun spear1340_clk_init(VA_MISC_BASE);
96*4882a593Smuzhiyun else
97*4882a593Smuzhiyun pr_err("%s: Unknown machine\n", __func__);
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
spear13xx_timer_init(void)100*4882a593Smuzhiyun void __init spear13xx_timer_init(void)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun char pclk_name[] = "osc_24m_clk";
103*4882a593Smuzhiyun struct clk *gpt_clk, *pclk;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun spear13xx_clk_init();
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun /* get the system timer clock */
108*4882a593Smuzhiyun gpt_clk = clk_get_sys("gpt0", NULL);
109*4882a593Smuzhiyun if (IS_ERR(gpt_clk)) {
110*4882a593Smuzhiyun pr_err("%s:couldn't get clk for gpt\n", __func__);
111*4882a593Smuzhiyun BUG();
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun /* get the suitable parent clock for timer*/
115*4882a593Smuzhiyun pclk = clk_get(NULL, pclk_name);
116*4882a593Smuzhiyun if (IS_ERR(pclk)) {
117*4882a593Smuzhiyun pr_err("%s:couldn't get %s as parent for gpt\n", __func__,
118*4882a593Smuzhiyun pclk_name);
119*4882a593Smuzhiyun BUG();
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun clk_set_parent(gpt_clk, pclk);
123*4882a593Smuzhiyun clk_put(gpt_clk);
124*4882a593Smuzhiyun clk_put(pclk);
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun spear_setup_of_timer();
127*4882a593Smuzhiyun timer_probe();
128*4882a593Smuzhiyun }
129