1*4882a593Smuzhiyun/* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * arch/arm/mach-spear13XX/headsmp.S 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Picked from realview 6*4882a593Smuzhiyun * Copyright (c) 2012 ST Microelectronics Limited 7*4882a593Smuzhiyun * Shiraz Hashim <shiraz.linux.kernel@gmail.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun#include <linux/linkage.h> 11*4882a593Smuzhiyun#include <linux/init.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun __INIT 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun/* 16*4882a593Smuzhiyun * spear13xx specific entry point for secondary CPUs. This provides 17*4882a593Smuzhiyun * a "holding pen" into which all secondary cores are held until we're 18*4882a593Smuzhiyun * ready for them to initialise. 19*4882a593Smuzhiyun */ 20*4882a593SmuzhiyunENTRY(spear13xx_secondary_startup) 21*4882a593Smuzhiyun mrc p15, 0, r0, c0, c0, 5 22*4882a593Smuzhiyun and r0, r0, #15 23*4882a593Smuzhiyun adr r4, 1f 24*4882a593Smuzhiyun ldmia r4, {r5, r6} 25*4882a593Smuzhiyun sub r4, r4, r5 26*4882a593Smuzhiyun add r6, r6, r4 27*4882a593Smuzhiyunpen: ldr r7, [r6] 28*4882a593Smuzhiyun cmp r7, r0 29*4882a593Smuzhiyun bne pen 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* re-enable coherency */ 32*4882a593Smuzhiyun mrc p15, 0, r0, c1, c0, 1 33*4882a593Smuzhiyun orr r0, r0, #(1 << 6) | (1 << 0) 34*4882a593Smuzhiyun mcr p15, 0, r0, c1, c0, 1 35*4882a593Smuzhiyun /* 36*4882a593Smuzhiyun * we've been released from the holding pen: secondary_stack 37*4882a593Smuzhiyun * should now contain the SVC stack for this core 38*4882a593Smuzhiyun */ 39*4882a593Smuzhiyun b secondary_startup 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun .align 42*4882a593Smuzhiyun1: .long . 43*4882a593Smuzhiyun .long spear_pen_release 44*4882a593SmuzhiyunENDPROC(spear13xx_secondary_startup) 45