1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright Altera Corporation (C) 2016. All rights reserved.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun #include <linux/io.h>
6*4882a593Smuzhiyun #include <linux/of_platform.h>
7*4882a593Smuzhiyun #include <linux/of_address.h>
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include "core.h"
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun /* A10 System Manager L2 ECC Control register */
12*4882a593Smuzhiyun #define A10_MPU_CTRL_L2_ECC_OFST 0x0
13*4882a593Smuzhiyun #define A10_MPU_CTRL_L2_ECC_EN BIT(0)
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun /* A10 System Manager Global IRQ Mask register */
16*4882a593Smuzhiyun #define A10_SYSMGR_ECC_INTMASK_CLR_OFST 0x98
17*4882a593Smuzhiyun #define A10_SYSMGR_ECC_INTMASK_CLR_L2 BIT(0)
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /* A10 System Manager L2 ECC IRQ Clear register */
20*4882a593Smuzhiyun #define A10_SYSMGR_MPU_CLEAR_L2_ECC_OFST 0xA8
21*4882a593Smuzhiyun #define A10_SYSMGR_MPU_CLEAR_L2_ECC (BIT(31) | BIT(15))
22*4882a593Smuzhiyun
socfpga_init_l2_ecc(void)23*4882a593Smuzhiyun void socfpga_init_l2_ecc(void)
24*4882a593Smuzhiyun {
25*4882a593Smuzhiyun struct device_node *np;
26*4882a593Smuzhiyun void __iomem *mapped_l2_edac_addr;
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun np = of_find_compatible_node(NULL, NULL, "altr,socfpga-l2-ecc");
29*4882a593Smuzhiyun if (!np) {
30*4882a593Smuzhiyun pr_err("Unable to find socfpga-l2-ecc in dtb\n");
31*4882a593Smuzhiyun return;
32*4882a593Smuzhiyun }
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun mapped_l2_edac_addr = of_iomap(np, 0);
35*4882a593Smuzhiyun of_node_put(np);
36*4882a593Smuzhiyun if (!mapped_l2_edac_addr) {
37*4882a593Smuzhiyun pr_err("Unable to find L2 ECC mapping in dtb\n");
38*4882a593Smuzhiyun return;
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /* Enable ECC */
42*4882a593Smuzhiyun writel(0x01, mapped_l2_edac_addr);
43*4882a593Smuzhiyun iounmap(mapped_l2_edac_addr);
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
socfpga_init_arria10_l2_ecc(void)46*4882a593Smuzhiyun void socfpga_init_arria10_l2_ecc(void)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun struct device_node *np;
49*4882a593Smuzhiyun void __iomem *mapped_l2_edac_addr;
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun /* Find the L2 EDAC device tree node */
52*4882a593Smuzhiyun np = of_find_compatible_node(NULL, NULL, "altr,socfpga-a10-l2-ecc");
53*4882a593Smuzhiyun if (!np) {
54*4882a593Smuzhiyun pr_err("Unable to find socfpga-a10-l2-ecc in dtb\n");
55*4882a593Smuzhiyun return;
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun mapped_l2_edac_addr = of_iomap(np, 0);
59*4882a593Smuzhiyun of_node_put(np);
60*4882a593Smuzhiyun if (!mapped_l2_edac_addr) {
61*4882a593Smuzhiyun pr_err("Unable to find L2 ECC mapping in dtb\n");
62*4882a593Smuzhiyun return;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun if (!sys_manager_base_addr) {
66*4882a593Smuzhiyun pr_err("System Manager not mapped for L2 ECC\n");
67*4882a593Smuzhiyun goto exit;
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun /* Clear any pending IRQs */
70*4882a593Smuzhiyun writel(A10_SYSMGR_MPU_CLEAR_L2_ECC, (sys_manager_base_addr +
71*4882a593Smuzhiyun A10_SYSMGR_MPU_CLEAR_L2_ECC_OFST));
72*4882a593Smuzhiyun /* Enable ECC */
73*4882a593Smuzhiyun writel(A10_SYSMGR_ECC_INTMASK_CLR_L2, sys_manager_base_addr +
74*4882a593Smuzhiyun A10_SYSMGR_ECC_INTMASK_CLR_OFST);
75*4882a593Smuzhiyun writel(A10_MPU_CTRL_L2_ECC_EN, mapped_l2_edac_addr +
76*4882a593Smuzhiyun A10_MPU_CTRL_L2_ECC_OFST);
77*4882a593Smuzhiyun exit:
78*4882a593Smuzhiyun iounmap(mapped_l2_edac_addr);
79*4882a593Smuzhiyun }
80