1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2012 Pavel Machek <pavel@denx.de> 4*4882a593Smuzhiyun * Copyright (C) 2012-2015 Altera Corporation 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __MACH_CORE_H 8*4882a593Smuzhiyun #define __MACH_CORE_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define SOCFPGA_RSTMGR_CTRL 0x04 11*4882a593Smuzhiyun #define SOCFPGA_RSTMGR_MODMPURST 0x10 12*4882a593Smuzhiyun #define SOCFPGA_RSTMGR_MODPERRST 0x14 13*4882a593Smuzhiyun #define SOCFPGA_RSTMGR_BRGMODRST 0x1c 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define SOCFPGA_A10_RSTMGR_CTRL 0xC 16*4882a593Smuzhiyun #define SOCFPGA_A10_RSTMGR_MODMPURST 0x20 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* System Manager bits */ 19*4882a593Smuzhiyun #define RSTMGR_CTRL_SWCOLDRSTREQ 0x1 /* Cold Reset */ 20*4882a593Smuzhiyun #define RSTMGR_CTRL_SWWARMRSTREQ 0x2 /* Warm Reset */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define RSTMGR_MPUMODRST_CPU1 0x2 /* CPU1 Reset */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun void socfpga_init_l2_ecc(void); 25*4882a593Smuzhiyun void socfpga_init_ocram_ecc(void); 26*4882a593Smuzhiyun void socfpga_init_arria10_l2_ecc(void); 27*4882a593Smuzhiyun void socfpga_init_arria10_ocram_ecc(void); 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun extern void __iomem *sys_manager_base_addr; 30*4882a593Smuzhiyun extern void __iomem *rst_manager_base_addr; 31*4882a593Smuzhiyun extern void __iomem *sdr_ctl_base_addr; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun u32 socfpga_sdram_self_refresh(u32 sdr_base); 34*4882a593Smuzhiyun extern unsigned int socfpga_sdram_self_refresh_sz; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun extern char secondary_trampoline[], secondary_trampoline_end[]; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun extern unsigned long socfpga_cpu1start_addr; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define SOCFPGA_SCU_VIRT_BASE 0xfee00000 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #endif 43