1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * r8a7779 processor support
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2011, 2013 Renesas Solutions Corp.
6*4882a593Smuzhiyun * Copyright (C) 2011 Magnus Damm
7*4882a593Smuzhiyun * Copyright (C) 2013 Cogent Embedded, Inc.
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun #include <linux/init.h>
10*4882a593Smuzhiyun #include <linux/irqchip.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <asm/mach/arch.h>
13*4882a593Smuzhiyun #include <asm/mach/map.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include "common.h"
16*4882a593Smuzhiyun #include "r8a7779.h"
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun static struct map_desc r8a7779_io_desc[] __initdata = {
19*4882a593Smuzhiyun /* 2M identity mapping for 0xf0000000 (MPCORE) */
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun .virtual = 0xf0000000,
22*4882a593Smuzhiyun .pfn = __phys_to_pfn(0xf0000000),
23*4882a593Smuzhiyun .length = SZ_2M,
24*4882a593Smuzhiyun .type = MT_DEVICE_NONSHARED
25*4882a593Smuzhiyun },
26*4882a593Smuzhiyun /* 16M identity mapping for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun .virtual = 0xfe000000,
29*4882a593Smuzhiyun .pfn = __phys_to_pfn(0xfe000000),
30*4882a593Smuzhiyun .length = SZ_16M,
31*4882a593Smuzhiyun .type = MT_DEVICE_NONSHARED
32*4882a593Smuzhiyun },
33*4882a593Smuzhiyun };
34*4882a593Smuzhiyun
r8a7779_map_io(void)35*4882a593Smuzhiyun static void __init r8a7779_map_io(void)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun debug_ll_io_init();
38*4882a593Smuzhiyun iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc));
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /* IRQ */
42*4882a593Smuzhiyun #define INT2SMSKCR0 IOMEM(0xfe7822a0)
43*4882a593Smuzhiyun #define INT2SMSKCR1 IOMEM(0xfe7822a4)
44*4882a593Smuzhiyun #define INT2SMSKCR2 IOMEM(0xfe7822a8)
45*4882a593Smuzhiyun #define INT2SMSKCR3 IOMEM(0xfe7822ac)
46*4882a593Smuzhiyun #define INT2SMSKCR4 IOMEM(0xfe7822b0)
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun #define INT2NTSR0 IOMEM(0xfe700060)
49*4882a593Smuzhiyun #define INT2NTSR1 IOMEM(0xfe700064)
50*4882a593Smuzhiyun
r8a7779_init_irq_dt(void)51*4882a593Smuzhiyun static void __init r8a7779_init_irq_dt(void)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun irqchip_init();
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /* route all interrupts to ARM */
56*4882a593Smuzhiyun __raw_writel(0xffffffff, INT2NTSR0);
57*4882a593Smuzhiyun __raw_writel(0x3fffffff, INT2NTSR1);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /* unmask all known interrupts in INTCS2 */
60*4882a593Smuzhiyun __raw_writel(0xfffffff0, INT2SMSKCR0);
61*4882a593Smuzhiyun __raw_writel(0xfff7ffff, INT2SMSKCR1);
62*4882a593Smuzhiyun __raw_writel(0xfffbffdf, INT2SMSKCR2);
63*4882a593Smuzhiyun __raw_writel(0xbffffffc, INT2SMSKCR3);
64*4882a593Smuzhiyun __raw_writel(0x003fee3f, INT2SMSKCR4);
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun static const char *const r8a7779_compat_dt[] __initconst = {
68*4882a593Smuzhiyun "renesas,r8a7779",
69*4882a593Smuzhiyun NULL,
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
73*4882a593Smuzhiyun .smp = smp_ops(r8a7779_smp_ops),
74*4882a593Smuzhiyun .map_io = r8a7779_map_io,
75*4882a593Smuzhiyun .init_irq = r8a7779_init_irq_dt,
76*4882a593Smuzhiyun .init_late = shmobile_init_late,
77*4882a593Smuzhiyun .dt_compat = r8a7779_compat_dt,
78*4882a593Smuzhiyun MACHINE_END
79