1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * R8A7740 processor support
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2011 Renesas Solutions Corp.
6*4882a593Smuzhiyun * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun #include <linux/kernel.h>
9*4882a593Smuzhiyun #include <linux/init.h>
10*4882a593Smuzhiyun #include <linux/io.h>
11*4882a593Smuzhiyun #include <linux/irqchip.h>
12*4882a593Smuzhiyun #include <linux/irqchip/arm-gic.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <asm/mach/map.h>
15*4882a593Smuzhiyun #include <asm/mach/arch.h>
16*4882a593Smuzhiyun #include <asm/mach/time.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include "common.h"
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun /*
21*4882a593Smuzhiyun * r8a7740 chip has lasting errata on MERAM buffer.
22*4882a593Smuzhiyun * this is work-around for it.
23*4882a593Smuzhiyun * see
24*4882a593Smuzhiyun * "Media RAM (MERAM)" on r8a7740 documentation
25*4882a593Smuzhiyun */
26*4882a593Smuzhiyun #define MEBUFCNTR 0xFE950098
r8a7740_meram_workaround(void)27*4882a593Smuzhiyun static void __init r8a7740_meram_workaround(void)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun void __iomem *reg;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun reg = ioremap(MEBUFCNTR, 4);
32*4882a593Smuzhiyun if (reg) {
33*4882a593Smuzhiyun iowrite32(0x01600164, reg);
34*4882a593Smuzhiyun iounmap(reg);
35*4882a593Smuzhiyun }
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun
r8a7740_init_irq_of(void)38*4882a593Smuzhiyun static void __init r8a7740_init_irq_of(void)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun void __iomem *intc_prio_base = ioremap(0xe6900010, 0x10);
41*4882a593Smuzhiyun void __iomem *intc_msk_base = ioremap(0xe6900040, 0x10);
42*4882a593Smuzhiyun void __iomem *pfc_inta_ctrl = ioremap(0xe605807c, 0x4);
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun irqchip_init();
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /* route signals to GIC */
47*4882a593Smuzhiyun iowrite32(0x0, pfc_inta_ctrl);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /*
50*4882a593Smuzhiyun * To mask the shared interrupt to SPI 149 we must ensure to set
51*4882a593Smuzhiyun * PRIO *and* MASK. Else we run into IRQ floods when registering
52*4882a593Smuzhiyun * the intc_irqpin devices
53*4882a593Smuzhiyun */
54*4882a593Smuzhiyun iowrite32(0x0, intc_prio_base + 0x0);
55*4882a593Smuzhiyun iowrite32(0x0, intc_prio_base + 0x4);
56*4882a593Smuzhiyun iowrite32(0x0, intc_prio_base + 0x8);
57*4882a593Smuzhiyun iowrite32(0x0, intc_prio_base + 0xc);
58*4882a593Smuzhiyun iowrite8(0xff, intc_msk_base + 0x0);
59*4882a593Smuzhiyun iowrite8(0xff, intc_msk_base + 0x4);
60*4882a593Smuzhiyun iowrite8(0xff, intc_msk_base + 0x8);
61*4882a593Smuzhiyun iowrite8(0xff, intc_msk_base + 0xc);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun iounmap(intc_prio_base);
64*4882a593Smuzhiyun iounmap(intc_msk_base);
65*4882a593Smuzhiyun iounmap(pfc_inta_ctrl);
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
r8a7740_generic_init(void)68*4882a593Smuzhiyun static void __init r8a7740_generic_init(void)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun r8a7740_meram_workaround();
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun static const char *const r8a7740_boards_compat_dt[] __initconst = {
74*4882a593Smuzhiyun "renesas,r8a7740",
75*4882a593Smuzhiyun NULL,
76*4882a593Smuzhiyun };
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
79*4882a593Smuzhiyun .l2c_aux_val = 0,
80*4882a593Smuzhiyun .l2c_aux_mask = ~0,
81*4882a593Smuzhiyun .init_early = shmobile_init_delay,
82*4882a593Smuzhiyun .init_irq = r8a7740_init_irq_of,
83*4882a593Smuzhiyun .init_machine = r8a7740_generic_init,
84*4882a593Smuzhiyun .init_late = shmobile_init_late,
85*4882a593Smuzhiyun .dt_compat = r8a7740_boards_compat_dt,
86*4882a593Smuzhiyun MACHINE_END
87