1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * R-Car Generation 2 da9063(L)/da9210 regulator quirk
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Certain Gen2 development boards have an da9063 and one or more da9210
6*4882a593Smuzhiyun * regulators. All of these regulators have their interrupt request lines
7*4882a593Smuzhiyun * tied to the same interrupt pin (IRQ2) on the SoC.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * After cold boot or da9063-induced restart, both the da9063 and da9210 seem
10*4882a593Smuzhiyun * to assert their interrupt request lines. Hence as soon as one driver
11*4882a593Smuzhiyun * requests this irq, it gets stuck in an interrupt storm, as it only manages
12*4882a593Smuzhiyun * to deassert its own interrupt request line, and the other driver hasn't
13*4882a593Smuzhiyun * installed an interrupt handler yet.
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun * To handle this, install a quirk that masks the interrupts in both the
16*4882a593Smuzhiyun * da9063 and da9210. This quirk has to run after the i2c master driver has
17*4882a593Smuzhiyun * been initialized, but before the i2c slave drivers are initialized.
18*4882a593Smuzhiyun *
19*4882a593Smuzhiyun * Copyright (C) 2015 Glider bvba
20*4882a593Smuzhiyun */
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #include <linux/device.h>
23*4882a593Smuzhiyun #include <linux/i2c.h>
24*4882a593Smuzhiyun #include <linux/init.h>
25*4882a593Smuzhiyun #include <linux/io.h>
26*4882a593Smuzhiyun #include <linux/list.h>
27*4882a593Smuzhiyun #include <linux/notifier.h>
28*4882a593Smuzhiyun #include <linux/of.h>
29*4882a593Smuzhiyun #include <linux/of_irq.h>
30*4882a593Smuzhiyun #include <linux/mfd/da9063/registers.h>
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #define IRQC_BASE 0xe61c0000
33*4882a593Smuzhiyun #define IRQC_MONITOR 0x104 /* IRQn Signal Level Monitor Register */
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun #define REGULATOR_IRQ_MASK BIT(2) /* IRQ2, active low */
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /* start of DA9210 System Control and Event Registers */
38*4882a593Smuzhiyun #define DA9210_REG_MASK_A 0x54
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun struct regulator_quirk {
41*4882a593Smuzhiyun struct list_head list;
42*4882a593Smuzhiyun const struct of_device_id *id;
43*4882a593Smuzhiyun struct device_node *np;
44*4882a593Smuzhiyun struct of_phandle_args irq_args;
45*4882a593Smuzhiyun struct i2c_msg i2c_msg;
46*4882a593Smuzhiyun bool shared; /* IRQ line is shared */
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun static LIST_HEAD(quirk_list);
50*4882a593Smuzhiyun static void __iomem *irqc;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /* first byte sets the memory pointer, following are consecutive reg values */
53*4882a593Smuzhiyun static u8 da9063_irq_clr[] = { DA9063_REG_IRQ_MASK_A, 0xff, 0xff, 0xff, 0xff };
54*4882a593Smuzhiyun static u8 da9210_irq_clr[] = { DA9210_REG_MASK_A, 0xff, 0xff };
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun static struct i2c_msg da9063_msg = {
57*4882a593Smuzhiyun .len = ARRAY_SIZE(da9063_irq_clr),
58*4882a593Smuzhiyun .buf = da9063_irq_clr,
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun static struct i2c_msg da9210_msg = {
62*4882a593Smuzhiyun .len = ARRAY_SIZE(da9210_irq_clr),
63*4882a593Smuzhiyun .buf = da9210_irq_clr,
64*4882a593Smuzhiyun };
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun static const struct of_device_id rcar_gen2_quirk_match[] = {
67*4882a593Smuzhiyun { .compatible = "dlg,da9063", .data = &da9063_msg },
68*4882a593Smuzhiyun { .compatible = "dlg,da9063l", .data = &da9063_msg },
69*4882a593Smuzhiyun { .compatible = "dlg,da9210", .data = &da9210_msg },
70*4882a593Smuzhiyun {},
71*4882a593Smuzhiyun };
72*4882a593Smuzhiyun
regulator_quirk_notify(struct notifier_block * nb,unsigned long action,void * data)73*4882a593Smuzhiyun static int regulator_quirk_notify(struct notifier_block *nb,
74*4882a593Smuzhiyun unsigned long action, void *data)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun struct regulator_quirk *pos, *tmp;
77*4882a593Smuzhiyun struct device *dev = data;
78*4882a593Smuzhiyun struct i2c_client *client;
79*4882a593Smuzhiyun static bool done;
80*4882a593Smuzhiyun int ret;
81*4882a593Smuzhiyun u32 mon;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun if (done)
84*4882a593Smuzhiyun return 0;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun mon = ioread32(irqc + IRQC_MONITOR);
87*4882a593Smuzhiyun dev_dbg(dev, "%s: %ld, IRQC_MONITOR = 0x%x\n", __func__, action, mon);
88*4882a593Smuzhiyun if (mon & REGULATOR_IRQ_MASK)
89*4882a593Smuzhiyun goto remove;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun if (action != BUS_NOTIFY_ADD_DEVICE || dev->type == &i2c_adapter_type)
92*4882a593Smuzhiyun return 0;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun client = to_i2c_client(dev);
95*4882a593Smuzhiyun dev_dbg(dev, "Detected %s\n", client->name);
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun /*
98*4882a593Smuzhiyun * Send message to all PMICs that share an IRQ line to deassert it.
99*4882a593Smuzhiyun *
100*4882a593Smuzhiyun * WARNING: This works only if all the PMICs are on the same I2C bus.
101*4882a593Smuzhiyun */
102*4882a593Smuzhiyun list_for_each_entry(pos, &quirk_list, list) {
103*4882a593Smuzhiyun if (!pos->shared)
104*4882a593Smuzhiyun continue;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun if (pos->np->parent != client->dev.parent->of_node)
107*4882a593Smuzhiyun continue;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun dev_info(&client->dev, "clearing %s@0x%02x interrupts\n",
110*4882a593Smuzhiyun pos->id->compatible, pos->i2c_msg.addr);
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun ret = i2c_transfer(client->adapter, &pos->i2c_msg, 1);
113*4882a593Smuzhiyun if (ret != 1)
114*4882a593Smuzhiyun dev_err(&client->dev, "i2c error %d\n", ret);
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun mon = ioread32(irqc + IRQC_MONITOR);
118*4882a593Smuzhiyun if (mon & REGULATOR_IRQ_MASK)
119*4882a593Smuzhiyun goto remove;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun return 0;
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun remove:
124*4882a593Smuzhiyun dev_info(dev, "IRQ2 is not asserted, removing quirk\n");
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun list_for_each_entry_safe(pos, tmp, &quirk_list, list) {
127*4882a593Smuzhiyun list_del(&pos->list);
128*4882a593Smuzhiyun of_node_put(pos->np);
129*4882a593Smuzhiyun kfree(pos);
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun done = true;
133*4882a593Smuzhiyun iounmap(irqc);
134*4882a593Smuzhiyun return 0;
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun static struct notifier_block regulator_quirk_nb = {
138*4882a593Smuzhiyun .notifier_call = regulator_quirk_notify
139*4882a593Smuzhiyun };
140*4882a593Smuzhiyun
rcar_gen2_regulator_quirk(void)141*4882a593Smuzhiyun static int __init rcar_gen2_regulator_quirk(void)
142*4882a593Smuzhiyun {
143*4882a593Smuzhiyun struct regulator_quirk *quirk, *pos, *tmp;
144*4882a593Smuzhiyun struct of_phandle_args *argsa, *argsb;
145*4882a593Smuzhiyun const struct of_device_id *id;
146*4882a593Smuzhiyun struct device_node *np;
147*4882a593Smuzhiyun u32 mon, addr;
148*4882a593Smuzhiyun int ret;
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun if (!of_machine_is_compatible("renesas,koelsch") &&
151*4882a593Smuzhiyun !of_machine_is_compatible("renesas,lager") &&
152*4882a593Smuzhiyun !of_machine_is_compatible("renesas,porter") &&
153*4882a593Smuzhiyun !of_machine_is_compatible("renesas,stout") &&
154*4882a593Smuzhiyun !of_machine_is_compatible("renesas,gose"))
155*4882a593Smuzhiyun return -ENODEV;
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun for_each_matching_node_and_match(np, rcar_gen2_quirk_match, &id) {
158*4882a593Smuzhiyun if (!of_device_is_available(np)) {
159*4882a593Smuzhiyun of_node_put(np);
160*4882a593Smuzhiyun break;
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun ret = of_property_read_u32(np, "reg", &addr);
164*4882a593Smuzhiyun if (ret) /* Skip invalid entry and continue */
165*4882a593Smuzhiyun continue;
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun quirk = kzalloc(sizeof(*quirk), GFP_KERNEL);
168*4882a593Smuzhiyun if (!quirk) {
169*4882a593Smuzhiyun ret = -ENOMEM;
170*4882a593Smuzhiyun of_node_put(np);
171*4882a593Smuzhiyun goto err_mem;
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun argsa = &quirk->irq_args;
175*4882a593Smuzhiyun memcpy(&quirk->i2c_msg, id->data, sizeof(quirk->i2c_msg));
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun quirk->id = id;
178*4882a593Smuzhiyun quirk->np = of_node_get(np);
179*4882a593Smuzhiyun quirk->i2c_msg.addr = addr;
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun ret = of_irq_parse_one(np, 0, argsa);
182*4882a593Smuzhiyun if (ret) { /* Skip invalid entry and continue */
183*4882a593Smuzhiyun of_node_put(np);
184*4882a593Smuzhiyun kfree(quirk);
185*4882a593Smuzhiyun continue;
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun list_for_each_entry(pos, &quirk_list, list) {
189*4882a593Smuzhiyun argsb = &pos->irq_args;
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun if (argsa->args_count != argsb->args_count)
192*4882a593Smuzhiyun continue;
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun ret = memcmp(argsa->args, argsb->args,
195*4882a593Smuzhiyun argsa->args_count *
196*4882a593Smuzhiyun sizeof(argsa->args[0]));
197*4882a593Smuzhiyun if (!ret) {
198*4882a593Smuzhiyun pos->shared = true;
199*4882a593Smuzhiyun quirk->shared = true;
200*4882a593Smuzhiyun }
201*4882a593Smuzhiyun }
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun list_add_tail(&quirk->list, &quirk_list);
204*4882a593Smuzhiyun }
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun irqc = ioremap(IRQC_BASE, PAGE_SIZE);
207*4882a593Smuzhiyun if (!irqc) {
208*4882a593Smuzhiyun ret = -ENOMEM;
209*4882a593Smuzhiyun goto err_mem;
210*4882a593Smuzhiyun }
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun mon = ioread32(irqc + IRQC_MONITOR);
213*4882a593Smuzhiyun if (mon & REGULATOR_IRQ_MASK) {
214*4882a593Smuzhiyun pr_debug("%s: IRQ2 is not asserted, not installing quirk\n",
215*4882a593Smuzhiyun __func__);
216*4882a593Smuzhiyun ret = 0;
217*4882a593Smuzhiyun goto err_free;
218*4882a593Smuzhiyun }
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun pr_info("IRQ2 is asserted, installing regulator quirk\n");
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun bus_register_notifier(&i2c_bus_type, ®ulator_quirk_nb);
223*4882a593Smuzhiyun return 0;
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun err_free:
226*4882a593Smuzhiyun iounmap(irqc);
227*4882a593Smuzhiyun err_mem:
228*4882a593Smuzhiyun list_for_each_entry_safe(pos, tmp, &quirk_list, list) {
229*4882a593Smuzhiyun list_del(&pos->list);
230*4882a593Smuzhiyun of_node_put(pos->np);
231*4882a593Smuzhiyun kfree(pos);
232*4882a593Smuzhiyun }
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun return ret;
235*4882a593Smuzhiyun }
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun arch_initcall(rcar_gen2_regulator_quirk);
238