1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * R-Car Generation 2 Power management support
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2013 - 2015 Renesas Electronics Corporation
6*4882a593Smuzhiyun * Copyright (C) 2011 Renesas Solutions Corp.
7*4882a593Smuzhiyun * Copyright (C) 2011 Magnus Damm
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/kernel.h>
11*4882a593Smuzhiyun #include <linux/ioport.h>
12*4882a593Smuzhiyun #include <linux/of.h>
13*4882a593Smuzhiyun #include <linux/of_address.h>
14*4882a593Smuzhiyun #include <linux/smp.h>
15*4882a593Smuzhiyun #include <asm/io.h>
16*4882a593Smuzhiyun #include <asm/cputype.h>
17*4882a593Smuzhiyun #include "common.h"
18*4882a593Smuzhiyun #include "rcar-gen2.h"
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun /* RST */
21*4882a593Smuzhiyun #define RST 0xe6160000
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define CA15BAR 0x0020 /* CA15 Boot Address Register */
24*4882a593Smuzhiyun #define CA7BAR 0x0030 /* CA7 Boot Address Register */
25*4882a593Smuzhiyun #define CA15RESCNT 0x0040 /* CA15 Reset Control Register */
26*4882a593Smuzhiyun #define CA7RESCNT 0x0044 /* CA7 Reset Control Register */
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /* SYS Boot Address Register */
29*4882a593Smuzhiyun #define SBAR_BAREN BIT(4) /* SBAR is valid */
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /* Reset Control Registers */
32*4882a593Smuzhiyun #define CA15RESCNT_CODE 0xa5a50000
33*4882a593Smuzhiyun #define CA15RESCNT_CPUS 0xf /* CPU0-3 */
34*4882a593Smuzhiyun #define CA7RESCNT_CODE 0x5a5a0000
35*4882a593Smuzhiyun #define CA7RESCNT_CPUS 0xf /* CPU0-3 */
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /* On-chip RAM */
38*4882a593Smuzhiyun #define ICRAM1 0xe63c0000 /* Inter Connect RAM1 (4 KiB) */
39*4882a593Smuzhiyun
phys_to_sbar(phys_addr_t addr)40*4882a593Smuzhiyun static inline u32 phys_to_sbar(phys_addr_t addr)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun return (addr >> 8) & 0xfffffc00;
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
rcar_gen2_pm_init(void)45*4882a593Smuzhiyun void __init rcar_gen2_pm_init(void)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun void __iomem *p;
48*4882a593Smuzhiyun u32 bar;
49*4882a593Smuzhiyun static int once;
50*4882a593Smuzhiyun struct device_node *np;
51*4882a593Smuzhiyun bool has_a7 = false;
52*4882a593Smuzhiyun bool has_a15 = false;
53*4882a593Smuzhiyun struct resource res;
54*4882a593Smuzhiyun int error;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun if (once++)
57*4882a593Smuzhiyun return;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun for_each_of_cpu_node(np) {
60*4882a593Smuzhiyun if (of_device_is_compatible(np, "arm,cortex-a15"))
61*4882a593Smuzhiyun has_a15 = true;
62*4882a593Smuzhiyun else if (of_device_is_compatible(np, "arm,cortex-a7"))
63*4882a593Smuzhiyun has_a7 = true;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun np = of_find_compatible_node(NULL, NULL, "renesas,smp-sram");
67*4882a593Smuzhiyun if (!np) {
68*4882a593Smuzhiyun /* No smp-sram in DT, fall back to hardcoded address */
69*4882a593Smuzhiyun res = (struct resource)DEFINE_RES_MEM(ICRAM1,
70*4882a593Smuzhiyun shmobile_boot_size);
71*4882a593Smuzhiyun goto map;
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun error = of_address_to_resource(np, 0, &res);
75*4882a593Smuzhiyun of_node_put(np);
76*4882a593Smuzhiyun if (error) {
77*4882a593Smuzhiyun pr_err("Failed to get smp-sram address: %d\n", error);
78*4882a593Smuzhiyun return;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun map:
82*4882a593Smuzhiyun /* RAM for jump stub, because BAR requires 256KB aligned address */
83*4882a593Smuzhiyun if (res.start & (256 * 1024 - 1) ||
84*4882a593Smuzhiyun resource_size(&res) < shmobile_boot_size) {
85*4882a593Smuzhiyun pr_err("Invalid smp-sram region\n");
86*4882a593Smuzhiyun return;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun p = ioremap(res.start, resource_size(&res));
90*4882a593Smuzhiyun if (!p)
91*4882a593Smuzhiyun return;
92*4882a593Smuzhiyun /*
93*4882a593Smuzhiyun * install the reset vector, use the largest version if we have enough
94*4882a593Smuzhiyun * memory available
95*4882a593Smuzhiyun */
96*4882a593Smuzhiyun if (resource_size(&res) >= shmobile_boot_size_gen2) {
97*4882a593Smuzhiyun shmobile_boot_cpu_gen2 = read_cpuid_mpidr();
98*4882a593Smuzhiyun memcpy_toio(p, shmobile_boot_vector_gen2,
99*4882a593Smuzhiyun shmobile_boot_size_gen2);
100*4882a593Smuzhiyun } else {
101*4882a593Smuzhiyun memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size);
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun iounmap(p);
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun /* setup reset vectors */
106*4882a593Smuzhiyun p = ioremap(RST, 0x63);
107*4882a593Smuzhiyun bar = phys_to_sbar(res.start);
108*4882a593Smuzhiyun if (has_a15) {
109*4882a593Smuzhiyun writel_relaxed(bar, p + CA15BAR);
110*4882a593Smuzhiyun writel_relaxed(bar | SBAR_BAREN, p + CA15BAR);
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun /* de-assert reset for CA15 CPUs */
113*4882a593Smuzhiyun writel_relaxed((readl_relaxed(p + CA15RESCNT) &
114*4882a593Smuzhiyun ~CA15RESCNT_CPUS) | CA15RESCNT_CODE,
115*4882a593Smuzhiyun p + CA15RESCNT);
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun if (has_a7) {
118*4882a593Smuzhiyun writel_relaxed(bar, p + CA7BAR);
119*4882a593Smuzhiyun writel_relaxed(bar | SBAR_BAREN, p + CA7BAR);
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun /* de-assert reset for CA7 CPUs */
122*4882a593Smuzhiyun writel_relaxed((readl_relaxed(p + CA7RESCNT) &
123*4882a593Smuzhiyun ~CA7RESCNT_CPUS) | CA7RESCNT_CODE,
124*4882a593Smuzhiyun p + CA7RESCNT);
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun iounmap(p);
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun shmobile_smp_apmu_suspend_init();
129*4882a593Smuzhiyun }
130