1*4882a593Smuzhiyun/* SPDX-License-Identifier: GPL-2.0+ 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Shared SCU setup for mach-shmobile 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2012 Bastian Hecht 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include <linux/linkage.h> 9*4882a593Smuzhiyun#include <linux/init.h> 10*4882a593Smuzhiyun#include <asm/memory.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/* 13*4882a593Smuzhiyun * Boot code for secondary CPUs. 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * First we turn on L1 cache coherency for our CPU. Then we jump to 16*4882a593Smuzhiyun * secondary_startup that invalidates the cache and hands over control 17*4882a593Smuzhiyun * to the common ARM startup code. 18*4882a593Smuzhiyun */ 19*4882a593SmuzhiyunENTRY(shmobile_boot_scu) 20*4882a593Smuzhiyun @ r0 = SCU base address 21*4882a593Smuzhiyun mrc p15, 0, r1, c0, c0, 5 @ read MPIDR 22*4882a593Smuzhiyun and r1, r1, #3 @ mask out cpu ID 23*4882a593Smuzhiyun lsl r1, r1, #3 @ we will shift by cpu_id * 8 bits 24*4882a593Smuzhiyun ldr r2, [r0, #8] @ SCU Power Status Register 25*4882a593Smuzhiyun mov r3, #3 26*4882a593Smuzhiyun lsl r3, r3, r1 27*4882a593Smuzhiyun bic r2, r2, r3 @ Clear bits of our CPU (Run Mode) 28*4882a593Smuzhiyun str r2, [r0, #8] @ write back 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun b secondary_startup 31*4882a593SmuzhiyunENDPROC(shmobile_boot_scu) 32