1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * SA1100 Power Management Routines
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or
7*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * History:
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * 2001-02-06: Cliff Brake Initial code
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * 2001-02-25: Sukjae Cho <sjcho@east.isi.edu> &
14*4882a593Smuzhiyun * Chester Kuo <chester@linux.org.tw>
15*4882a593Smuzhiyun * Save more value for the resume function! Support
16*4882a593Smuzhiyun * Bitsy/Assabet/Freebird board
17*4882a593Smuzhiyun *
18*4882a593Smuzhiyun * 2001-08-29: Nicolas Pitre <nico@fluxnic.net>
19*4882a593Smuzhiyun * Cleaned up, pushed platform dependent stuff
20*4882a593Smuzhiyun * in the platform specific files.
21*4882a593Smuzhiyun *
22*4882a593Smuzhiyun * 2002-05-27: Nicolas Pitre Killed sleep.h and the kmalloced save array.
23*4882a593Smuzhiyun * Storage is local on the stack now.
24*4882a593Smuzhiyun */
25*4882a593Smuzhiyun #include <linux/init.h>
26*4882a593Smuzhiyun #include <linux/io.h>
27*4882a593Smuzhiyun #include <linux/suspend.h>
28*4882a593Smuzhiyun #include <linux/errno.h>
29*4882a593Smuzhiyun #include <linux/time.h>
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #include <mach/hardware.h>
32*4882a593Smuzhiyun #include <asm/memory.h>
33*4882a593Smuzhiyun #include <asm/suspend.h>
34*4882a593Smuzhiyun #include <asm/mach/time.h>
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun extern int sa1100_finish_suspend(unsigned long);
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
39*4882a593Smuzhiyun #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /*
42*4882a593Smuzhiyun * List of global SA11x0 peripheral registers to preserve.
43*4882a593Smuzhiyun * More ones like CP and general purpose register values are preserved
44*4882a593Smuzhiyun * on the stack and then the stack pointer is stored last in sleep.S.
45*4882a593Smuzhiyun */
46*4882a593Smuzhiyun enum { SLEEP_SAVE_GPDR, SLEEP_SAVE_GAFR,
47*4882a593Smuzhiyun SLEEP_SAVE_PPDR, SLEEP_SAVE_PPSR, SLEEP_SAVE_PPAR, SLEEP_SAVE_PSDR,
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun SLEEP_SAVE_Ser1SDCR0,
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun SLEEP_SAVE_COUNT
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun
sa11x0_pm_enter(suspend_state_t state)55*4882a593Smuzhiyun static int sa11x0_pm_enter(suspend_state_t state)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun unsigned long gpio, sleep_save[SLEEP_SAVE_COUNT];
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun gpio = GPLR;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /* save vital registers */
62*4882a593Smuzhiyun SAVE(GPDR);
63*4882a593Smuzhiyun SAVE(GAFR);
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun SAVE(PPDR);
66*4882a593Smuzhiyun SAVE(PPSR);
67*4882a593Smuzhiyun SAVE(PPAR);
68*4882a593Smuzhiyun SAVE(PSDR);
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun SAVE(Ser1SDCR0);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun /* Clear previous reset status */
73*4882a593Smuzhiyun RCSR = RCSR_HWR | RCSR_SWR | RCSR_WDR | RCSR_SMR;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /* set resume return address */
76*4882a593Smuzhiyun PSPR = __pa_symbol(cpu_resume);
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /* go zzz */
79*4882a593Smuzhiyun cpu_suspend(0, sa1100_finish_suspend);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun /*
82*4882a593Smuzhiyun * Ensure not to come back here if it wasn't intended
83*4882a593Smuzhiyun */
84*4882a593Smuzhiyun RCSR = RCSR_SMR;
85*4882a593Smuzhiyun PSPR = 0;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /*
88*4882a593Smuzhiyun * Ensure interrupt sources are disabled; we will re-init
89*4882a593Smuzhiyun * the interrupt subsystem via the device manager.
90*4882a593Smuzhiyun */
91*4882a593Smuzhiyun ICLR = 0;
92*4882a593Smuzhiyun ICCR = 1;
93*4882a593Smuzhiyun ICMR = 0;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun /* restore registers */
96*4882a593Smuzhiyun RESTORE(GPDR);
97*4882a593Smuzhiyun RESTORE(GAFR);
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun RESTORE(PPDR);
100*4882a593Smuzhiyun RESTORE(PPSR);
101*4882a593Smuzhiyun RESTORE(PPAR);
102*4882a593Smuzhiyun RESTORE(PSDR);
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun RESTORE(Ser1SDCR0);
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun GPSR = gpio;
107*4882a593Smuzhiyun GPCR = ~gpio;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun /*
110*4882a593Smuzhiyun * Clear the peripheral sleep-hold bit.
111*4882a593Smuzhiyun */
112*4882a593Smuzhiyun PSSR = PSSR_PH;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun return 0;
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun static const struct platform_suspend_ops sa11x0_pm_ops = {
118*4882a593Smuzhiyun .enter = sa11x0_pm_enter,
119*4882a593Smuzhiyun .valid = suspend_valid_only_mem,
120*4882a593Smuzhiyun };
121*4882a593Smuzhiyun
sa11x0_pm_init(void)122*4882a593Smuzhiyun int __init sa11x0_pm_init(void)
123*4882a593Smuzhiyun {
124*4882a593Smuzhiyun suspend_set_ops(&sa11x0_pm_ops);
125*4882a593Smuzhiyun return 0;
126*4882a593Smuzhiyun }
127