xref: /OK3568_Linux_fs/kernel/arch/arm/mach-sa1100/neponset.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * linux/arch/arm/mach-sa1100/neponset.c
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun #include <linux/err.h>
6*4882a593Smuzhiyun #include <linux/gpio/driver.h>
7*4882a593Smuzhiyun #include <linux/gpio/gpio-reg.h>
8*4882a593Smuzhiyun #include <linux/gpio/machine.h>
9*4882a593Smuzhiyun #include <linux/init.h>
10*4882a593Smuzhiyun #include <linux/ioport.h>
11*4882a593Smuzhiyun #include <linux/irq.h>
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <linux/platform_device.h>
15*4882a593Smuzhiyun #include <linux/pm.h>
16*4882a593Smuzhiyun #include <linux/serial_core.h>
17*4882a593Smuzhiyun #include <linux/slab.h>
18*4882a593Smuzhiyun #include <linux/smc91x.h>
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #include <asm/mach-types.h>
21*4882a593Smuzhiyun #include <asm/mach/map.h>
22*4882a593Smuzhiyun #include <asm/hardware/sa1111.h>
23*4882a593Smuzhiyun #include <linux/sizes.h>
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun #include <mach/hardware.h>
26*4882a593Smuzhiyun #include <mach/assabet.h>
27*4882a593Smuzhiyun #include <mach/neponset.h>
28*4882a593Smuzhiyun #include <mach/irqs.h>
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun #define NEP_IRQ_SMC91X	0
31*4882a593Smuzhiyun #define NEP_IRQ_USAR	1
32*4882a593Smuzhiyun #define NEP_IRQ_SA1111	2
33*4882a593Smuzhiyun #define NEP_IRQ_NR	3
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun #define WHOAMI		0x00
36*4882a593Smuzhiyun #define LEDS		0x10
37*4882a593Smuzhiyun #define SWPK		0x20
38*4882a593Smuzhiyun #define IRR		0x24
39*4882a593Smuzhiyun #define KP_Y_IN		0x80
40*4882a593Smuzhiyun #define KP_X_OUT	0x90
41*4882a593Smuzhiyun #define NCR_0		0xa0
42*4882a593Smuzhiyun #define MDM_CTL_0	0xb0
43*4882a593Smuzhiyun #define MDM_CTL_1	0xb4
44*4882a593Smuzhiyun #define AUD_CTL		0xc0
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun #define IRR_ETHERNET	(1 << 0)
47*4882a593Smuzhiyun #define IRR_USAR	(1 << 1)
48*4882a593Smuzhiyun #define IRR_SA1111	(1 << 2)
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun #define NCR_NGPIO	7
51*4882a593Smuzhiyun #define MDM_CTL0_NGPIO	4
52*4882a593Smuzhiyun #define MDM_CTL1_NGPIO	6
53*4882a593Smuzhiyun #define AUD_NGPIO	2
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun extern void sa1110_mb_disable(void);
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun #define to_neponset_gpio_chip(x) container_of(x, struct neponset_gpio_chip, gc)
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun static const char *neponset_ncr_names[] = {
60*4882a593Smuzhiyun 	"gp01_off", "tp_power", "ms_power", "enet_osc",
61*4882a593Smuzhiyun 	"spi_kb_wk_up", "a0vpp", "a1vpp"
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun static const char *neponset_mdmctl0_names[] = {
65*4882a593Smuzhiyun 	"rts3", "dtr3", "rts1", "dtr1",
66*4882a593Smuzhiyun };
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun static const char *neponset_mdmctl1_names[] = {
69*4882a593Smuzhiyun 	"cts3", "dsr3", "dcd3", "cts1", "dsr1", "dcd1"
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun static const char *neponset_aud_names[] = {
73*4882a593Smuzhiyun 	"sel_1341", "mute_1341",
74*4882a593Smuzhiyun };
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun struct neponset_drvdata {
77*4882a593Smuzhiyun 	void __iomem *base;
78*4882a593Smuzhiyun 	struct platform_device *sa1111;
79*4882a593Smuzhiyun 	struct platform_device *smc91x;
80*4882a593Smuzhiyun 	unsigned irq_base;
81*4882a593Smuzhiyun 	struct gpio_chip *gpio[4];
82*4882a593Smuzhiyun };
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun static struct gpiod_lookup_table neponset_uart1_gpio_table = {
85*4882a593Smuzhiyun 	.dev_id = "sa11x0-uart.1",
86*4882a593Smuzhiyun 	.table = {
87*4882a593Smuzhiyun 		GPIO_LOOKUP("neponset-mdm-ctl0", 2, "rts", GPIO_ACTIVE_LOW),
88*4882a593Smuzhiyun 		GPIO_LOOKUP("neponset-mdm-ctl0", 3, "dtr", GPIO_ACTIVE_LOW),
89*4882a593Smuzhiyun 		GPIO_LOOKUP("neponset-mdm-ctl1", 3, "cts", GPIO_ACTIVE_LOW),
90*4882a593Smuzhiyun 		GPIO_LOOKUP("neponset-mdm-ctl1", 4, "dsr", GPIO_ACTIVE_LOW),
91*4882a593Smuzhiyun 		GPIO_LOOKUP("neponset-mdm-ctl1", 5, "dcd", GPIO_ACTIVE_LOW),
92*4882a593Smuzhiyun 		{ },
93*4882a593Smuzhiyun 	},
94*4882a593Smuzhiyun };
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun static struct gpiod_lookup_table neponset_uart3_gpio_table = {
97*4882a593Smuzhiyun 	.dev_id = "sa11x0-uart.3",
98*4882a593Smuzhiyun 	.table = {
99*4882a593Smuzhiyun 		GPIO_LOOKUP("neponset-mdm-ctl0", 0, "rts", GPIO_ACTIVE_LOW),
100*4882a593Smuzhiyun 		GPIO_LOOKUP("neponset-mdm-ctl0", 1, "dtr", GPIO_ACTIVE_LOW),
101*4882a593Smuzhiyun 		GPIO_LOOKUP("neponset-mdm-ctl1", 0, "cts", GPIO_ACTIVE_LOW),
102*4882a593Smuzhiyun 		GPIO_LOOKUP("neponset-mdm-ctl1", 1, "dsr", GPIO_ACTIVE_LOW),
103*4882a593Smuzhiyun 		GPIO_LOOKUP("neponset-mdm-ctl1", 2, "dcd", GPIO_ACTIVE_LOW),
104*4882a593Smuzhiyun 		{ },
105*4882a593Smuzhiyun 	},
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun static struct gpiod_lookup_table neponset_pcmcia_table = {
109*4882a593Smuzhiyun 	.dev_id = "1800",
110*4882a593Smuzhiyun 	.table = {
111*4882a593Smuzhiyun 		GPIO_LOOKUP("sa1111", 1, "a0vcc", GPIO_ACTIVE_HIGH),
112*4882a593Smuzhiyun 		GPIO_LOOKUP("sa1111", 0, "a1vcc", GPIO_ACTIVE_HIGH),
113*4882a593Smuzhiyun 		GPIO_LOOKUP("neponset-ncr", 5, "a0vpp", GPIO_ACTIVE_HIGH),
114*4882a593Smuzhiyun 		GPIO_LOOKUP("neponset-ncr", 6, "a1vpp", GPIO_ACTIVE_HIGH),
115*4882a593Smuzhiyun 		GPIO_LOOKUP("sa1111", 2, "b0vcc", GPIO_ACTIVE_HIGH),
116*4882a593Smuzhiyun 		GPIO_LOOKUP("sa1111", 3, "b1vcc", GPIO_ACTIVE_HIGH),
117*4882a593Smuzhiyun 		{ },
118*4882a593Smuzhiyun 	},
119*4882a593Smuzhiyun };
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun static struct neponset_drvdata *nep;
122*4882a593Smuzhiyun 
neponset_ncr_frob(unsigned int mask,unsigned int val)123*4882a593Smuzhiyun void neponset_ncr_frob(unsigned int mask, unsigned int val)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun 	struct neponset_drvdata *n = nep;
126*4882a593Smuzhiyun 	unsigned long m = mask, v = val;
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	if (nep)
129*4882a593Smuzhiyun 		n->gpio[0]->set_multiple(n->gpio[0], &m, &v);
130*4882a593Smuzhiyun 	else
131*4882a593Smuzhiyun 		WARN(1, "nep unset\n");
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun EXPORT_SYMBOL(neponset_ncr_frob);
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun /*
136*4882a593Smuzhiyun  * Install handler for Neponset IRQ.  Note that we have to loop here
137*4882a593Smuzhiyun  * since the ETHERNET and USAR IRQs are level based, and we need to
138*4882a593Smuzhiyun  * ensure that the IRQ signal is deasserted before returning.  This
139*4882a593Smuzhiyun  * is rather unfortunate.
140*4882a593Smuzhiyun  */
neponset_irq_handler(struct irq_desc * desc)141*4882a593Smuzhiyun static void neponset_irq_handler(struct irq_desc *desc)
142*4882a593Smuzhiyun {
143*4882a593Smuzhiyun 	struct neponset_drvdata *d = irq_desc_get_handler_data(desc);
144*4882a593Smuzhiyun 	unsigned int irr;
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun 	while (1) {
147*4882a593Smuzhiyun 		/*
148*4882a593Smuzhiyun 		 * Acknowledge the parent IRQ.
149*4882a593Smuzhiyun 		 */
150*4882a593Smuzhiyun 		desc->irq_data.chip->irq_ack(&desc->irq_data);
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 		/*
153*4882a593Smuzhiyun 		 * Read the interrupt reason register.  Let's have all
154*4882a593Smuzhiyun 		 * active IRQ bits high.  Note: there is a typo in the
155*4882a593Smuzhiyun 		 * Neponset user's guide for the SA1111 IRR level.
156*4882a593Smuzhiyun 		 */
157*4882a593Smuzhiyun 		irr = readb_relaxed(d->base + IRR);
158*4882a593Smuzhiyun 		irr ^= IRR_ETHERNET | IRR_USAR;
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 		if ((irr & (IRR_ETHERNET | IRR_USAR | IRR_SA1111)) == 0)
161*4882a593Smuzhiyun 			break;
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 		/*
164*4882a593Smuzhiyun 		 * Since there is no individual mask, we have to
165*4882a593Smuzhiyun 		 * mask the parent IRQ.  This is safe, since we'll
166*4882a593Smuzhiyun 		 * recheck the register for any pending IRQs.
167*4882a593Smuzhiyun 		 */
168*4882a593Smuzhiyun 		if (irr & (IRR_ETHERNET | IRR_USAR)) {
169*4882a593Smuzhiyun 			desc->irq_data.chip->irq_mask(&desc->irq_data);
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun 			/*
172*4882a593Smuzhiyun 			 * Ack the interrupt now to prevent re-entering
173*4882a593Smuzhiyun 			 * this neponset handler.  Again, this is safe
174*4882a593Smuzhiyun 			 * since we'll check the IRR register prior to
175*4882a593Smuzhiyun 			 * leaving.
176*4882a593Smuzhiyun 			 */
177*4882a593Smuzhiyun 			desc->irq_data.chip->irq_ack(&desc->irq_data);
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun 			if (irr & IRR_ETHERNET)
180*4882a593Smuzhiyun 				generic_handle_irq(d->irq_base + NEP_IRQ_SMC91X);
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun 			if (irr & IRR_USAR)
183*4882a593Smuzhiyun 				generic_handle_irq(d->irq_base + NEP_IRQ_USAR);
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 			desc->irq_data.chip->irq_unmask(&desc->irq_data);
186*4882a593Smuzhiyun 		}
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun 		if (irr & IRR_SA1111)
189*4882a593Smuzhiyun 			generic_handle_irq(d->irq_base + NEP_IRQ_SA1111);
190*4882a593Smuzhiyun 	}
191*4882a593Smuzhiyun }
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun /* Yes, we really do not have any kind of masking or unmasking */
nochip_noop(struct irq_data * irq)194*4882a593Smuzhiyun static void nochip_noop(struct irq_data *irq)
195*4882a593Smuzhiyun {
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun static struct irq_chip nochip = {
199*4882a593Smuzhiyun 	.name = "neponset",
200*4882a593Smuzhiyun 	.irq_ack = nochip_noop,
201*4882a593Smuzhiyun 	.irq_mask = nochip_noop,
202*4882a593Smuzhiyun 	.irq_unmask = nochip_noop,
203*4882a593Smuzhiyun };
204*4882a593Smuzhiyun 
neponset_init_gpio(struct gpio_chip ** gcp,struct device * dev,const char * label,void __iomem * reg,unsigned num,bool in,const char * const * names)205*4882a593Smuzhiyun static int neponset_init_gpio(struct gpio_chip **gcp,
206*4882a593Smuzhiyun 	struct device *dev, const char *label, void __iomem *reg,
207*4882a593Smuzhiyun 	unsigned num, bool in, const char *const * names)
208*4882a593Smuzhiyun {
209*4882a593Smuzhiyun 	struct gpio_chip *gc;
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 	gc = gpio_reg_init(dev, reg, -1, num, label, in ? 0xffffffff : 0,
212*4882a593Smuzhiyun 			   readl_relaxed(reg), names, NULL, NULL);
213*4882a593Smuzhiyun 	if (IS_ERR(gc))
214*4882a593Smuzhiyun 		return PTR_ERR(gc);
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun 	*gcp = gc;
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun 	return 0;
219*4882a593Smuzhiyun }
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun static struct sa1111_platform_data sa1111_info = {
222*4882a593Smuzhiyun 	.disable_devs	= SA1111_DEVID_PS2_MSE,
223*4882a593Smuzhiyun };
224*4882a593Smuzhiyun 
neponset_probe(struct platform_device * dev)225*4882a593Smuzhiyun static int neponset_probe(struct platform_device *dev)
226*4882a593Smuzhiyun {
227*4882a593Smuzhiyun 	struct neponset_drvdata *d;
228*4882a593Smuzhiyun 	struct resource *nep_res, *sa1111_res, *smc91x_res;
229*4882a593Smuzhiyun 	struct resource sa1111_resources[] = {
230*4882a593Smuzhiyun 		DEFINE_RES_MEM(0x40000000, SZ_8K),
231*4882a593Smuzhiyun 		{ .flags = IORESOURCE_IRQ },
232*4882a593Smuzhiyun 	};
233*4882a593Smuzhiyun 	struct platform_device_info sa1111_devinfo = {
234*4882a593Smuzhiyun 		.parent = &dev->dev,
235*4882a593Smuzhiyun 		.name = "sa1111",
236*4882a593Smuzhiyun 		.id = 0,
237*4882a593Smuzhiyun 		.res = sa1111_resources,
238*4882a593Smuzhiyun 		.num_res = ARRAY_SIZE(sa1111_resources),
239*4882a593Smuzhiyun 		.data = &sa1111_info,
240*4882a593Smuzhiyun 		.size_data = sizeof(sa1111_info),
241*4882a593Smuzhiyun 		.dma_mask = 0xffffffffUL,
242*4882a593Smuzhiyun 	};
243*4882a593Smuzhiyun 	struct resource smc91x_resources[] = {
244*4882a593Smuzhiyun 		DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS,
245*4882a593Smuzhiyun 			0x02000000, "smc91x-regs"),
246*4882a593Smuzhiyun 		DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS + 0x02000000,
247*4882a593Smuzhiyun 			0x02000000, "smc91x-attrib"),
248*4882a593Smuzhiyun 		{ .flags = IORESOURCE_IRQ },
249*4882a593Smuzhiyun 	};
250*4882a593Smuzhiyun 	struct smc91x_platdata smc91x_platdata = {
251*4882a593Smuzhiyun 		.flags = SMC91X_USE_8BIT | SMC91X_IO_SHIFT_2 | SMC91X_NOWAIT,
252*4882a593Smuzhiyun 	};
253*4882a593Smuzhiyun 	struct platform_device_info smc91x_devinfo = {
254*4882a593Smuzhiyun 		.parent = &dev->dev,
255*4882a593Smuzhiyun 		.name = "smc91x",
256*4882a593Smuzhiyun 		.id = 0,
257*4882a593Smuzhiyun 		.res = smc91x_resources,
258*4882a593Smuzhiyun 		.num_res = ARRAY_SIZE(smc91x_resources),
259*4882a593Smuzhiyun 		.data = &smc91x_platdata,
260*4882a593Smuzhiyun 		.size_data = sizeof(smc91x_platdata),
261*4882a593Smuzhiyun 	};
262*4882a593Smuzhiyun 	int ret, irq;
263*4882a593Smuzhiyun 
264*4882a593Smuzhiyun 	if (nep)
265*4882a593Smuzhiyun 		return -EBUSY;
266*4882a593Smuzhiyun 
267*4882a593Smuzhiyun 	irq = ret = platform_get_irq(dev, 0);
268*4882a593Smuzhiyun 	if (ret < 0)
269*4882a593Smuzhiyun 		goto err_alloc;
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun 	nep_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
272*4882a593Smuzhiyun 	smc91x_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
273*4882a593Smuzhiyun 	sa1111_res = platform_get_resource(dev, IORESOURCE_MEM, 2);
274*4882a593Smuzhiyun 	if (!nep_res || !smc91x_res || !sa1111_res) {
275*4882a593Smuzhiyun 		ret = -ENXIO;
276*4882a593Smuzhiyun 		goto err_alloc;
277*4882a593Smuzhiyun 	}
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun 	d = kzalloc(sizeof(*d), GFP_KERNEL);
280*4882a593Smuzhiyun 	if (!d) {
281*4882a593Smuzhiyun 		ret = -ENOMEM;
282*4882a593Smuzhiyun 		goto err_alloc;
283*4882a593Smuzhiyun 	}
284*4882a593Smuzhiyun 
285*4882a593Smuzhiyun 	d->base = ioremap(nep_res->start, SZ_4K);
286*4882a593Smuzhiyun 	if (!d->base) {
287*4882a593Smuzhiyun 		ret = -ENOMEM;
288*4882a593Smuzhiyun 		goto err_ioremap;
289*4882a593Smuzhiyun 	}
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun 	if (readb_relaxed(d->base + WHOAMI) != 0x11) {
292*4882a593Smuzhiyun 		dev_warn(&dev->dev, "Neponset board detected, but wrong ID: %02x\n",
293*4882a593Smuzhiyun 			 readb_relaxed(d->base + WHOAMI));
294*4882a593Smuzhiyun 		ret = -ENODEV;
295*4882a593Smuzhiyun 		goto err_id;
296*4882a593Smuzhiyun 	}
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun 	ret = irq_alloc_descs(-1, IRQ_BOARD_START, NEP_IRQ_NR, -1);
299*4882a593Smuzhiyun 	if (ret <= 0) {
300*4882a593Smuzhiyun 		dev_err(&dev->dev, "unable to allocate %u irqs: %d\n",
301*4882a593Smuzhiyun 			NEP_IRQ_NR, ret);
302*4882a593Smuzhiyun 		if (ret == 0)
303*4882a593Smuzhiyun 			ret = -ENOMEM;
304*4882a593Smuzhiyun 		goto err_irq_alloc;
305*4882a593Smuzhiyun 	}
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun 	d->irq_base = ret;
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun 	irq_set_chip_and_handler(d->irq_base + NEP_IRQ_SMC91X, &nochip,
310*4882a593Smuzhiyun 		handle_simple_irq);
311*4882a593Smuzhiyun 	irq_clear_status_flags(d->irq_base + NEP_IRQ_SMC91X, IRQ_NOREQUEST | IRQ_NOPROBE);
312*4882a593Smuzhiyun 	irq_set_chip_and_handler(d->irq_base + NEP_IRQ_USAR, &nochip,
313*4882a593Smuzhiyun 		handle_simple_irq);
314*4882a593Smuzhiyun 	irq_clear_status_flags(d->irq_base + NEP_IRQ_USAR, IRQ_NOREQUEST | IRQ_NOPROBE);
315*4882a593Smuzhiyun 	irq_set_chip(d->irq_base + NEP_IRQ_SA1111, &nochip);
316*4882a593Smuzhiyun 
317*4882a593Smuzhiyun 	irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
318*4882a593Smuzhiyun 	irq_set_chained_handler_and_data(irq, neponset_irq_handler, d);
319*4882a593Smuzhiyun 
320*4882a593Smuzhiyun 	/* Disable GPIO 0/1 drivers so the buttons work on the Assabet */
321*4882a593Smuzhiyun 	writeb_relaxed(NCR_GP01_OFF, d->base + NCR_0);
322*4882a593Smuzhiyun 
323*4882a593Smuzhiyun 	neponset_init_gpio(&d->gpio[0], &dev->dev, "neponset-ncr",
324*4882a593Smuzhiyun 			   d->base + NCR_0, NCR_NGPIO, false,
325*4882a593Smuzhiyun 			   neponset_ncr_names);
326*4882a593Smuzhiyun 	neponset_init_gpio(&d->gpio[1], &dev->dev, "neponset-mdm-ctl0",
327*4882a593Smuzhiyun 			   d->base + MDM_CTL_0, MDM_CTL0_NGPIO, false,
328*4882a593Smuzhiyun 			   neponset_mdmctl0_names);
329*4882a593Smuzhiyun 	neponset_init_gpio(&d->gpio[2], &dev->dev, "neponset-mdm-ctl1",
330*4882a593Smuzhiyun 			   d->base + MDM_CTL_1, MDM_CTL1_NGPIO, true,
331*4882a593Smuzhiyun 			   neponset_mdmctl1_names);
332*4882a593Smuzhiyun 	neponset_init_gpio(&d->gpio[3], &dev->dev, "neponset-aud-ctl",
333*4882a593Smuzhiyun 			   d->base + AUD_CTL, AUD_NGPIO, false,
334*4882a593Smuzhiyun 			   neponset_aud_names);
335*4882a593Smuzhiyun 
336*4882a593Smuzhiyun 	gpiod_add_lookup_table(&neponset_uart1_gpio_table);
337*4882a593Smuzhiyun 	gpiod_add_lookup_table(&neponset_uart3_gpio_table);
338*4882a593Smuzhiyun 	gpiod_add_lookup_table(&neponset_pcmcia_table);
339*4882a593Smuzhiyun 
340*4882a593Smuzhiyun 	/*
341*4882a593Smuzhiyun 	 * We would set IRQ_GPIO25 to be a wake-up IRQ, but unfortunately
342*4882a593Smuzhiyun 	 * something on the Neponset activates this IRQ on sleep (eth?)
343*4882a593Smuzhiyun 	 */
344*4882a593Smuzhiyun #if 0
345*4882a593Smuzhiyun 	enable_irq_wake(irq);
346*4882a593Smuzhiyun #endif
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun 	dev_info(&dev->dev, "Neponset daughter board, providing IRQ%u-%u\n",
349*4882a593Smuzhiyun 		 d->irq_base, d->irq_base + NEP_IRQ_NR - 1);
350*4882a593Smuzhiyun 	nep = d;
351*4882a593Smuzhiyun 
352*4882a593Smuzhiyun 	/* Ensure that the memory bus request/grant signals are setup */
353*4882a593Smuzhiyun 	sa1110_mb_disable();
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun 	sa1111_resources[0].parent = sa1111_res;
356*4882a593Smuzhiyun 	sa1111_resources[1].start = d->irq_base + NEP_IRQ_SA1111;
357*4882a593Smuzhiyun 	sa1111_resources[1].end = d->irq_base + NEP_IRQ_SA1111;
358*4882a593Smuzhiyun 	d->sa1111 = platform_device_register_full(&sa1111_devinfo);
359*4882a593Smuzhiyun 
360*4882a593Smuzhiyun 	smc91x_resources[0].parent = smc91x_res;
361*4882a593Smuzhiyun 	smc91x_resources[1].parent = smc91x_res;
362*4882a593Smuzhiyun 	smc91x_resources[2].start = d->irq_base + NEP_IRQ_SMC91X;
363*4882a593Smuzhiyun 	smc91x_resources[2].end = d->irq_base + NEP_IRQ_SMC91X;
364*4882a593Smuzhiyun 	d->smc91x = platform_device_register_full(&smc91x_devinfo);
365*4882a593Smuzhiyun 
366*4882a593Smuzhiyun 	platform_set_drvdata(dev, d);
367*4882a593Smuzhiyun 
368*4882a593Smuzhiyun 	return 0;
369*4882a593Smuzhiyun 
370*4882a593Smuzhiyun  err_irq_alloc:
371*4882a593Smuzhiyun  err_id:
372*4882a593Smuzhiyun 	iounmap(d->base);
373*4882a593Smuzhiyun  err_ioremap:
374*4882a593Smuzhiyun 	kfree(d);
375*4882a593Smuzhiyun  err_alloc:
376*4882a593Smuzhiyun 	return ret;
377*4882a593Smuzhiyun }
378*4882a593Smuzhiyun 
neponset_remove(struct platform_device * dev)379*4882a593Smuzhiyun static int neponset_remove(struct platform_device *dev)
380*4882a593Smuzhiyun {
381*4882a593Smuzhiyun 	struct neponset_drvdata *d = platform_get_drvdata(dev);
382*4882a593Smuzhiyun 	int irq = platform_get_irq(dev, 0);
383*4882a593Smuzhiyun 
384*4882a593Smuzhiyun 	if (!IS_ERR(d->sa1111))
385*4882a593Smuzhiyun 		platform_device_unregister(d->sa1111);
386*4882a593Smuzhiyun 	if (!IS_ERR(d->smc91x))
387*4882a593Smuzhiyun 		platform_device_unregister(d->smc91x);
388*4882a593Smuzhiyun 
389*4882a593Smuzhiyun 	gpiod_remove_lookup_table(&neponset_pcmcia_table);
390*4882a593Smuzhiyun 	gpiod_remove_lookup_table(&neponset_uart3_gpio_table);
391*4882a593Smuzhiyun 	gpiod_remove_lookup_table(&neponset_uart1_gpio_table);
392*4882a593Smuzhiyun 
393*4882a593Smuzhiyun 	irq_set_chained_handler(irq, NULL);
394*4882a593Smuzhiyun 	irq_free_descs(d->irq_base, NEP_IRQ_NR);
395*4882a593Smuzhiyun 	nep = NULL;
396*4882a593Smuzhiyun 	iounmap(d->base);
397*4882a593Smuzhiyun 	kfree(d);
398*4882a593Smuzhiyun 
399*4882a593Smuzhiyun 	return 0;
400*4882a593Smuzhiyun }
401*4882a593Smuzhiyun 
402*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
neponset_resume(struct device * dev)403*4882a593Smuzhiyun static int neponset_resume(struct device *dev)
404*4882a593Smuzhiyun {
405*4882a593Smuzhiyun 	struct neponset_drvdata *d = dev_get_drvdata(dev);
406*4882a593Smuzhiyun 	int i, ret = 0;
407*4882a593Smuzhiyun 
408*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(d->gpio); i++) {
409*4882a593Smuzhiyun 		ret = gpio_reg_resume(d->gpio[i]);
410*4882a593Smuzhiyun 		if (ret)
411*4882a593Smuzhiyun 			break;
412*4882a593Smuzhiyun 	}
413*4882a593Smuzhiyun 
414*4882a593Smuzhiyun 	return ret;
415*4882a593Smuzhiyun }
416*4882a593Smuzhiyun 
417*4882a593Smuzhiyun static const struct dev_pm_ops neponset_pm_ops = {
418*4882a593Smuzhiyun 	.resume_noirq = neponset_resume,
419*4882a593Smuzhiyun 	.restore_noirq = neponset_resume,
420*4882a593Smuzhiyun };
421*4882a593Smuzhiyun #define PM_OPS &neponset_pm_ops
422*4882a593Smuzhiyun #else
423*4882a593Smuzhiyun #define PM_OPS NULL
424*4882a593Smuzhiyun #endif
425*4882a593Smuzhiyun 
426*4882a593Smuzhiyun static struct platform_driver neponset_device_driver = {
427*4882a593Smuzhiyun 	.probe		= neponset_probe,
428*4882a593Smuzhiyun 	.remove		= neponset_remove,
429*4882a593Smuzhiyun 	.driver		= {
430*4882a593Smuzhiyun 		.name	= "neponset",
431*4882a593Smuzhiyun 		.pm	= PM_OPS,
432*4882a593Smuzhiyun 	},
433*4882a593Smuzhiyun };
434*4882a593Smuzhiyun 
neponset_init(void)435*4882a593Smuzhiyun static int __init neponset_init(void)
436*4882a593Smuzhiyun {
437*4882a593Smuzhiyun 	return platform_driver_register(&neponset_device_driver);
438*4882a593Smuzhiyun }
439*4882a593Smuzhiyun 
440*4882a593Smuzhiyun subsys_initcall(neponset_init);
441