1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef _INCLUDE_SHANNON_H 3*4882a593Smuzhiyun #define _INCLUDE_SHANNON_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* taken from comp.os.inferno Tue, 12 Sep 2000 09:21:50 GMT, 6*4882a593Smuzhiyun * written by <forsyth@vitanuova.com> */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #define SHANNON_GPIO_SPI_FLASH GPIO_GPIO (0) /* Output - Driven low, enables SPI to flash */ 9*4882a593Smuzhiyun #define SHANNON_GPIO_SPI_DSP GPIO_GPIO (1) /* Output - Driven low, enables SPI to DSP */ 10*4882a593Smuzhiyun /* lcd lower = GPIO 2-9 */ 11*4882a593Smuzhiyun #define SHANNON_GPIO_SPI_OUTPUT GPIO_GPIO (10) /* Output - SPI output to DSP */ 12*4882a593Smuzhiyun #define SHANNON_GPIO_SPI_INPUT GPIO_GPIO (11) /* Input - SPI input from DSP */ 13*4882a593Smuzhiyun #define SHANNON_GPIO_SPI_CLOCK GPIO_GPIO (12) /* Output - Clock for SPI */ 14*4882a593Smuzhiyun #define SHANNON_GPIO_SPI_FRAME GPIO_GPIO (13) /* Output - Frame marker - not used */ 15*4882a593Smuzhiyun #define SHANNON_GPIO_SPI_RTS GPIO_GPIO (14) /* Input - SPI Ready to Send */ 16*4882a593Smuzhiyun #define SHANNON_IRQ_GPIO_SPI_RTS IRQ_GPIO14 17*4882a593Smuzhiyun #define SHANNON_GPIO_SPI_CTS GPIO_GPIO (15) /* Output - SPI Clear to Send */ 18*4882a593Smuzhiyun #define SHANNON_GPIO_IRQ_CODEC GPIO_GPIO (16) /* in, irq from ucb1200 */ 19*4882a593Smuzhiyun #define SHANNON_IRQ_GPIO_IRQ_CODEC IRQ_GPIO16 20*4882a593Smuzhiyun #define SHANNON_GPIO_DSP_RESET GPIO_GPIO (17) /* Output - Drive low to reset the DSP */ 21*4882a593Smuzhiyun #define SHANNON_GPIO_CODEC_RESET GPIO_GPIO (18) /* Output - Drive low to reset the UCB1x00 */ 22*4882a593Smuzhiyun #define SHANNON_GPIO_U3_RTS GPIO_GPIO (19) /* ?? */ 23*4882a593Smuzhiyun #define SHANNON_GPIO_U3_CTS GPIO_GPIO (20) /* ?? */ 24*4882a593Smuzhiyun #define SHANNON_GPIO_SENSE_12V GPIO_GPIO (21) /* Input, 12v flash unprotect detected */ 25*4882a593Smuzhiyun #define SHANNON_GPIO_DISP_EN 22 /* out */ 26*4882a593Smuzhiyun /* XXX GPIO 23 unaccounted for */ 27*4882a593Smuzhiyun #define SHANNON_GPIO_EJECT_0 24 /* in */ 28*4882a593Smuzhiyun #define SHANNON_GPIO_EJECT_1 25 /* in */ 29*4882a593Smuzhiyun #define SHANNON_GPIO_RDY_0 26 /* in */ 30*4882a593Smuzhiyun #define SHANNON_GPIO_RDY_1 27 /* in */ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* MCP UCB codec GPIO pins... */ 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define SHANNON_UCB_GPIO_BACKLIGHT 9 35*4882a593Smuzhiyun #define SHANNON_UCB_GPIO_BRIGHT_MASK 7 36*4882a593Smuzhiyun #define SHANNON_UCB_GPIO_BRIGHT 6 37*4882a593Smuzhiyun #define SHANNON_UCB_GPIO_CONTRAST_MASK 0x3f 38*4882a593Smuzhiyun #define SHANNON_UCB_GPIO_CONTRAST 0 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #endif 41