1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __ASM_ARCH_RESET_H 3*4882a593Smuzhiyun #define __ASM_ARCH_RESET_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include "hardware.h" 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #define RESET_STATUS_HARDWARE (1 << 0) /* Hardware Reset */ 8*4882a593Smuzhiyun #define RESET_STATUS_WATCHDOG (1 << 1) /* Watchdog Reset */ 9*4882a593Smuzhiyun #define RESET_STATUS_LOWPOWER (1 << 2) /* Exit from Low Power/Sleep */ 10*4882a593Smuzhiyun #define RESET_STATUS_GPIO (1 << 3) /* GPIO Reset */ 11*4882a593Smuzhiyun #define RESET_STATUS_ALL (0xf) 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun extern unsigned int reset_status; clear_reset_status(unsigned int mask)14*4882a593Smuzhiyunstatic inline void clear_reset_status(unsigned int mask) 15*4882a593Smuzhiyun { 16*4882a593Smuzhiyun RCSR = mask; 17*4882a593Smuzhiyun } 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #endif /* __ASM_ARCH_RESET_H */ 20