1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * arch/arm/mach-sa1100/include/mach/nanoengine.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This file contains the hardware specific definitions for nanoEngine. 6*4882a593Smuzhiyun * Only include this file from SA1100-specific files. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br> 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun #ifndef __ASM_ARCH_NANOENGINE_H 11*4882a593Smuzhiyun #define __ASM_ARCH_NANOENGINE_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <mach/irqs.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define GPIO_PC_READY0 11 /* ready for socket 0 (active high)*/ 16*4882a593Smuzhiyun #define GPIO_PC_READY1 12 /* ready for socket 1 (active high) */ 17*4882a593Smuzhiyun #define GPIO_PC_CD0 13 /* detect for socket 0 (active low) */ 18*4882a593Smuzhiyun #define GPIO_PC_CD1 14 /* detect for socket 1 (active low) */ 19*4882a593Smuzhiyun #define GPIO_PC_RESET0 15 /* reset socket 0 */ 20*4882a593Smuzhiyun #define GPIO_PC_RESET1 16 /* reset socket 1 */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define NANOENGINE_IRQ_GPIO_PCI IRQ_GPIO0 23*4882a593Smuzhiyun #define NANOENGINE_IRQ_GPIO_PC_READY0 IRQ_GPIO11 24*4882a593Smuzhiyun #define NANOENGINE_IRQ_GPIO_PC_READY1 IRQ_GPIO12 25*4882a593Smuzhiyun #define NANOENGINE_IRQ_GPIO_PC_CD0 IRQ_GPIO13 26*4882a593Smuzhiyun #define NANOENGINE_IRQ_GPIO_PC_CD1 IRQ_GPIO14 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* 29*4882a593Smuzhiyun * nanoEngine Memory Map: 30*4882a593Smuzhiyun * 31*4882a593Smuzhiyun * 0000.0000 - 003F.0000 - 4 MB Flash 32*4882a593Smuzhiyun * C000.0000 - C1FF.FFFF - 32 MB SDRAM 33*4882a593Smuzhiyun * 1860.0000 - 186F.FFFF - 1 MB Internal PCI Memory Read/Write 34*4882a593Smuzhiyun * 18A1.0000 - 18A1.FFFF - 64 KB Internal PCI Config Space 35*4882a593Smuzhiyun * 4000.0000 - 47FF.FFFF - 128 MB External Bus I/O - Multiplexed Mode 36*4882a593Smuzhiyun * 4800.0000 - 4FFF.FFFF - 128 MB External Bus I/O - Non-Multiplexed Mode 37*4882a593Smuzhiyun * 38*4882a593Smuzhiyun */ 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define NANO_PCI_MEM_RW_PHYS 0x18600000 41*4882a593Smuzhiyun #define NANO_PCI_MEM_RW_VIRT 0xf1000000 42*4882a593Smuzhiyun #define NANO_PCI_MEM_RW_SIZE SZ_1M 43*4882a593Smuzhiyun #define NANO_PCI_CONFIG_SPACE_PHYS 0x18A10000 44*4882a593Smuzhiyun #define NANO_PCI_CONFIG_SPACE_VIRT 0xf2000000 45*4882a593Smuzhiyun #define NANO_PCI_CONFIG_SPACE_SIZE SZ_64K 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #endif 48*4882a593Smuzhiyun 49