1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * arch/arm/mach-sa1100/include/mach/irqs.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 1996 Russell King 6*4882a593Smuzhiyun * Copyright (C) 1998 Deborah Wallach (updates for SA1100/Brutus). 7*4882a593Smuzhiyun * Copyright (C) 1999 Nicolas Pitre (full GPIO irq isolation) 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * 2001/11/14 RMK Cleaned up and standardised a lot of the IRQs. 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define IRQ_GPIO0_SC 1 13*4882a593Smuzhiyun #define IRQ_GPIO1_SC 2 14*4882a593Smuzhiyun #define IRQ_GPIO2_SC 3 15*4882a593Smuzhiyun #define IRQ_GPIO3_SC 4 16*4882a593Smuzhiyun #define IRQ_GPIO4_SC 5 17*4882a593Smuzhiyun #define IRQ_GPIO5_SC 6 18*4882a593Smuzhiyun #define IRQ_GPIO6_SC 7 19*4882a593Smuzhiyun #define IRQ_GPIO7_SC 8 20*4882a593Smuzhiyun #define IRQ_GPIO8_SC 9 21*4882a593Smuzhiyun #define IRQ_GPIO9_SC 10 22*4882a593Smuzhiyun #define IRQ_GPIO10_SC 11 23*4882a593Smuzhiyun #define IRQ_GPIO11_27 12 24*4882a593Smuzhiyun #define IRQ_LCD 13 /* LCD controller */ 25*4882a593Smuzhiyun #define IRQ_Ser0UDC 14 /* Ser. port 0 UDC */ 26*4882a593Smuzhiyun #define IRQ_Ser1SDLC 15 /* Ser. port 1 SDLC */ 27*4882a593Smuzhiyun #define IRQ_Ser1UART 16 /* Ser. port 1 UART */ 28*4882a593Smuzhiyun #define IRQ_Ser2ICP 17 /* Ser. port 2 ICP */ 29*4882a593Smuzhiyun #define IRQ_Ser3UART 18 /* Ser. port 3 UART */ 30*4882a593Smuzhiyun #define IRQ_Ser4MCP 19 /* Ser. port 4 MCP */ 31*4882a593Smuzhiyun #define IRQ_Ser4SSP 20 /* Ser. port 4 SSP */ 32*4882a593Smuzhiyun #define IRQ_DMA0 21 /* DMA controller channel 0 */ 33*4882a593Smuzhiyun #define IRQ_DMA1 22 /* DMA controller channel 1 */ 34*4882a593Smuzhiyun #define IRQ_DMA2 23 /* DMA controller channel 2 */ 35*4882a593Smuzhiyun #define IRQ_DMA3 24 /* DMA controller channel 3 */ 36*4882a593Smuzhiyun #define IRQ_DMA4 25 /* DMA controller channel 4 */ 37*4882a593Smuzhiyun #define IRQ_DMA5 26 /* DMA controller channel 5 */ 38*4882a593Smuzhiyun #define IRQ_OST0 27 /* OS Timer match 0 */ 39*4882a593Smuzhiyun #define IRQ_OST1 28 /* OS Timer match 1 */ 40*4882a593Smuzhiyun #define IRQ_OST2 29 /* OS Timer match 2 */ 41*4882a593Smuzhiyun #define IRQ_OST3 30 /* OS Timer match 3 */ 42*4882a593Smuzhiyun #define IRQ_RTC1Hz 31 /* RTC 1 Hz clock */ 43*4882a593Smuzhiyun #define IRQ_RTCAlrm 32 /* RTC Alarm */ 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define IRQ_GPIO0 33 46*4882a593Smuzhiyun #define IRQ_GPIO1 34 47*4882a593Smuzhiyun #define IRQ_GPIO2 35 48*4882a593Smuzhiyun #define IRQ_GPIO3 36 49*4882a593Smuzhiyun #define IRQ_GPIO4 37 50*4882a593Smuzhiyun #define IRQ_GPIO5 38 51*4882a593Smuzhiyun #define IRQ_GPIO6 39 52*4882a593Smuzhiyun #define IRQ_GPIO7 40 53*4882a593Smuzhiyun #define IRQ_GPIO8 41 54*4882a593Smuzhiyun #define IRQ_GPIO9 42 55*4882a593Smuzhiyun #define IRQ_GPIO10 43 56*4882a593Smuzhiyun #define IRQ_GPIO11 44 57*4882a593Smuzhiyun #define IRQ_GPIO12 45 58*4882a593Smuzhiyun #define IRQ_GPIO13 46 59*4882a593Smuzhiyun #define IRQ_GPIO14 47 60*4882a593Smuzhiyun #define IRQ_GPIO15 48 61*4882a593Smuzhiyun #define IRQ_GPIO16 49 62*4882a593Smuzhiyun #define IRQ_GPIO17 50 63*4882a593Smuzhiyun #define IRQ_GPIO18 51 64*4882a593Smuzhiyun #define IRQ_GPIO19 52 65*4882a593Smuzhiyun #define IRQ_GPIO20 53 66*4882a593Smuzhiyun #define IRQ_GPIO21 54 67*4882a593Smuzhiyun #define IRQ_GPIO22 55 68*4882a593Smuzhiyun #define IRQ_GPIO23 56 69*4882a593Smuzhiyun #define IRQ_GPIO24 57 70*4882a593Smuzhiyun #define IRQ_GPIO25 58 71*4882a593Smuzhiyun #define IRQ_GPIO26 59 72*4882a593Smuzhiyun #define IRQ_GPIO27 60 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* 75*4882a593Smuzhiyun * The next 16 interrupts are for board specific purposes. Since 76*4882a593Smuzhiyun * the kernel can only run on one machine at a time, we can re-use 77*4882a593Smuzhiyun * these. If you need more, increase IRQ_BOARD_END, but keep it 78*4882a593Smuzhiyun * within sensible limits. IRQs 61 to 76 are available. 79*4882a593Smuzhiyun */ 80*4882a593Smuzhiyun #define IRQ_BOARD_START 61 81*4882a593Smuzhiyun #define IRQ_BOARD_END 77 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* 84*4882a593Smuzhiyun * Figure out the MAX IRQ number. 85*4882a593Smuzhiyun * 86*4882a593Smuzhiyun * Neponset, SA1111 and UCB1x00 are sparse IRQ aware, so can dynamically 87*4882a593Smuzhiyun * allocate their IRQs above NR_IRQS. 88*4882a593Smuzhiyun * 89*4882a593Smuzhiyun * LoCoMo has 4 additional IRQs, but is not sparse IRQ aware, and so has 90*4882a593Smuzhiyun * to be included in the NR_IRQS calculation. 91*4882a593Smuzhiyun */ 92*4882a593Smuzhiyun #ifdef CONFIG_SHARP_LOCOMO 93*4882a593Smuzhiyun #define NR_IRQS_LOCOMO 4 94*4882a593Smuzhiyun #else 95*4882a593Smuzhiyun #define NR_IRQS_LOCOMO 0 96*4882a593Smuzhiyun #endif 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #ifndef NR_IRQS 99*4882a593Smuzhiyun #define NR_IRQS (IRQ_BOARD_START + NR_IRQS_LOCOMO) 100*4882a593Smuzhiyun #endif 101*4882a593Smuzhiyun #define SA1100_NR_IRQS (IRQ_BOARD_START + NR_IRQS_LOCOMO) 102