1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * arch/arm/mach-sa1100/include/mach/collie.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This file contains the hardware specific definitions for Collie 6*4882a593Smuzhiyun * Only include this file from SA1100-specific files. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * ChangeLog: 9*4882a593Smuzhiyun * 04-06-2001 Lineo Japan, Inc. 10*4882a593Smuzhiyun * 04-16-2001 SHARP Corporation 11*4882a593Smuzhiyun * 07-07-2002 Chris Larson <clarson@digi.com> 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun #ifndef __ASM_ARCH_COLLIE_H 15*4882a593Smuzhiyun #define __ASM_ARCH_COLLIE_H 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #include "hardware.h" /* Gives GPIO_MAX */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun extern void locomolcd_power(int on); 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define COLLIE_SCOOP_GPIO_BASE (GPIO_MAX + 1) 22*4882a593Smuzhiyun #define COLLIE_GPIO_CHARGE_ON (COLLIE_SCOOP_GPIO_BASE + 0) 23*4882a593Smuzhiyun #define COLLIE_SCP_DIAG_BOOT1 SCOOP_GPCR_PA12 24*4882a593Smuzhiyun #define COLLIE_SCP_DIAG_BOOT2 SCOOP_GPCR_PA13 25*4882a593Smuzhiyun #define COLLIE_SCP_MUTE_L SCOOP_GPCR_PA14 26*4882a593Smuzhiyun #define COLLIE_SCP_MUTE_R SCOOP_GPCR_PA15 27*4882a593Smuzhiyun #define COLLIE_SCP_5VON SCOOP_GPCR_PA16 28*4882a593Smuzhiyun #define COLLIE_SCP_AMP_ON SCOOP_GPCR_PA17 29*4882a593Smuzhiyun #define COLLIE_GPIO_VPEN (COLLIE_SCOOP_GPIO_BASE + 7) 30*4882a593Smuzhiyun #define COLLIE_SCP_LB_VOL_CHG SCOOP_GPCR_PA19 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define COLLIE_SCOOP_IO_DIR (COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R | \ 33*4882a593Smuzhiyun COLLIE_SCP_5VON | COLLIE_SCP_AMP_ON | \ 34*4882a593Smuzhiyun COLLIE_SCP_LB_VOL_CHG) 35*4882a593Smuzhiyun #define COLLIE_SCOOP_IO_OUT (COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* GPIOs for gpiolib */ 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define COLLIE_GPIO_ON_KEY (0) 40*4882a593Smuzhiyun #define COLLIE_GPIO_AC_IN (1) 41*4882a593Smuzhiyun #define COLLIE_GPIO_SDIO_INT (11) 42*4882a593Smuzhiyun #define COLLIE_GPIO_CF_IRQ (14) 43*4882a593Smuzhiyun #define COLLIE_GPIO_nREMOCON_INT (15) 44*4882a593Smuzhiyun #define COLLIE_GPIO_UCB1x00_RESET (16) 45*4882a593Smuzhiyun #define COLLIE_GPIO_nMIC_ON (17) 46*4882a593Smuzhiyun #define COLLIE_GPIO_nREMOCON_ON (18) 47*4882a593Smuzhiyun #define COLLIE_GPIO_CO (20) 48*4882a593Smuzhiyun #define COLLIE_GPIO_MCP_CLK (21) 49*4882a593Smuzhiyun #define COLLIE_GPIO_CF_CD (22) 50*4882a593Smuzhiyun #define COLLIE_GPIO_UCB1x00_IRQ (23) 51*4882a593Smuzhiyun #define COLLIE_GPIO_WAKEUP (24) 52*4882a593Smuzhiyun #define COLLIE_GPIO_GA_INT (25) 53*4882a593Smuzhiyun #define COLLIE_GPIO_MAIN_BAT_LOW (26) 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* GPIO definitions for direct register access */ 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define _COLLIE_GPIO_ON_KEY GPIO_GPIO(0) 58*4882a593Smuzhiyun #define _COLLIE_GPIO_AC_IN GPIO_GPIO(1) 59*4882a593Smuzhiyun #define _COLLIE_GPIO_nREMOCON_INT GPIO_GPIO(15) 60*4882a593Smuzhiyun #define _COLLIE_GPIO_UCB1x00_RESET GPIO_GPIO(16) 61*4882a593Smuzhiyun #define _COLLIE_GPIO_nMIC_ON GPIO_GPIO(17) 62*4882a593Smuzhiyun #define _COLLIE_GPIO_nREMOCON_ON GPIO_GPIO(18) 63*4882a593Smuzhiyun #define _COLLIE_GPIO_CO GPIO_GPIO(20) 64*4882a593Smuzhiyun #define _COLLIE_GPIO_WAKEUP GPIO_GPIO(24) 65*4882a593Smuzhiyun /* Interrupts */ 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define COLLIE_IRQ_GPIO_ON_KEY IRQ_GPIO0 68*4882a593Smuzhiyun #define COLLIE_IRQ_GPIO_AC_IN IRQ_GPIO1 69*4882a593Smuzhiyun #define COLLIE_IRQ_GPIO_SDIO_IRQ IRQ_GPIO11 70*4882a593Smuzhiyun #define COLLIE_IRQ_GPIO_CF_IRQ IRQ_GPIO14 71*4882a593Smuzhiyun #define COLLIE_IRQ_GPIO_nREMOCON_INT IRQ_GPIO15 72*4882a593Smuzhiyun #define COLLIE_IRQ_GPIO_CO IRQ_GPIO20 73*4882a593Smuzhiyun #define COLLIE_IRQ_GPIO_CF_CD IRQ_GPIO22 74*4882a593Smuzhiyun #define COLLIE_IRQ_GPIO_UCB1x00_IRQ IRQ_GPIO23 75*4882a593Smuzhiyun #define COLLIE_IRQ_GPIO_WAKEUP IRQ_GPIO24 76*4882a593Smuzhiyun #define COLLIE_IRQ_GPIO_GA_INT IRQ_GPIO25 77*4882a593Smuzhiyun #define COLLIE_IRQ_GPIO_MAIN_BAT_LOW IRQ_GPIO26 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* GPIO's on the TC35143AF (Toshiba Analog Frontend) */ 80*4882a593Smuzhiyun #define COLLIE_TC35143_GPIO_BASE (GPIO_MAX + 13) 81*4882a593Smuzhiyun #define COLLIE_TC35143_GPIO_VERSION0 UCB_IO_0 82*4882a593Smuzhiyun #define COLLIE_TC35143_GPIO_TBL_CHK UCB_IO_1 83*4882a593Smuzhiyun #define COLLIE_TC35143_GPIO_VPEN_ON UCB_IO_2 84*4882a593Smuzhiyun #define COLLIE_GPIO_IR_ON (COLLIE_TC35143_GPIO_BASE + 3) 85*4882a593Smuzhiyun #define COLLIE_TC35143_GPIO_AMP_ON UCB_IO_4 86*4882a593Smuzhiyun #define COLLIE_TC35143_GPIO_VERSION1 UCB_IO_5 87*4882a593Smuzhiyun #define COLLIE_TC35143_GPIO_FS8KLPF UCB_IO_5 88*4882a593Smuzhiyun #define COLLIE_TC35143_GPIO_BUZZER_BIAS UCB_IO_6 89*4882a593Smuzhiyun #define COLLIE_GPIO_MBAT_ON (COLLIE_TC35143_GPIO_BASE + 7) 90*4882a593Smuzhiyun #define COLLIE_GPIO_BBAT_ON (COLLIE_TC35143_GPIO_BASE + 8) 91*4882a593Smuzhiyun #define COLLIE_GPIO_TMP_ON (COLLIE_TC35143_GPIO_BASE + 9) 92*4882a593Smuzhiyun #define COLLIE_TC35143_GPIO_IN (UCB_IO_0 | UCB_IO_2 | UCB_IO_5) 93*4882a593Smuzhiyun #define COLLIE_TC35143_GPIO_OUT (UCB_IO_1 | UCB_IO_3 | UCB_IO_4 \ 94*4882a593Smuzhiyun | UCB_IO_6) 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun #endif 97