1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * arch/arm/mach-sa1100/include/mach/badge4.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Tim Connors <connors@hpl.hp.com> 6*4882a593Smuzhiyun * Christopher Hoover <ch@hpl.hp.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Copyright (C) 2002 Hewlett-Packard Company 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __ASM_ARCH_HARDWARE_H 12*4882a593Smuzhiyun #error "include <mach/hardware.h> instead" 13*4882a593Smuzhiyun #endif 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define BADGE4_SA1111_BASE (0x48000000) 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* GPIOs on the BadgePAD 4 */ 18*4882a593Smuzhiyun #define BADGE4_GPIO_INT_1111 GPIO_GPIO0 /* SA-1111 IRQ */ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define BADGE4_GPIO_INT_VID GPIO_GPIO1 /* Video expansion */ 21*4882a593Smuzhiyun #define BADGE4_GPIO_LGP2 GPIO_GPIO2 /* GPIO_LDD8 */ 22*4882a593Smuzhiyun #define BADGE4_GPIO_LGP3 GPIO_GPIO3 /* GPIO_LDD9 */ 23*4882a593Smuzhiyun #define BADGE4_GPIO_LGP4 GPIO_GPIO4 /* GPIO_LDD10 */ 24*4882a593Smuzhiyun #define BADGE4_GPIO_LGP5 GPIO_GPIO5 /* GPIO_LDD11 */ 25*4882a593Smuzhiyun #define BADGE4_GPIO_LGP6 GPIO_GPIO6 /* GPIO_LDD12 */ 26*4882a593Smuzhiyun #define BADGE4_GPIO_LGP7 GPIO_GPIO7 /* GPIO_LDD13 */ 27*4882a593Smuzhiyun #define BADGE4_GPIO_LGP8 GPIO_GPIO8 /* GPIO_LDD14 */ 28*4882a593Smuzhiyun #define BADGE4_GPIO_LGP9 GPIO_GPIO9 /* GPIO_LDD15 */ 29*4882a593Smuzhiyun #define BADGE4_GPIO_GPA_VID GPIO_GPIO10 /* Video expansion */ 30*4882a593Smuzhiyun #define BADGE4_GPIO_GPB_VID GPIO_GPIO11 /* Video expansion */ 31*4882a593Smuzhiyun #define BADGE4_GPIO_GPC_VID GPIO_GPIO12 /* Video expansion */ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define BADGE4_GPIO_UART_HS1 GPIO_GPIO13 34*4882a593Smuzhiyun #define BADGE4_GPIO_UART_HS2 GPIO_GPIO14 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define BADGE4_GPIO_MUXSEL0 GPIO_GPIO15 37*4882a593Smuzhiyun #define BADGE4_GPIO_TESTPT_J7 GPIO_GPIO16 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define BADGE4_GPIO_SDSDA GPIO_GPIO17 /* SDRAM SPD Data */ 40*4882a593Smuzhiyun #define BADGE4_GPIO_SDSCL GPIO_GPIO18 /* SDRAM SPD Clock */ 41*4882a593Smuzhiyun #define BADGE4_GPIO_SDTYP0 GPIO_GPIO19 /* SDRAM Type Control */ 42*4882a593Smuzhiyun #define BADGE4_GPIO_SDTYP1 GPIO_GPIO20 /* SDRAM Type Control */ 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define BADGE4_GPIO_BGNT_1111 GPIO_GPIO21 /* GPIO_MBGNT */ 45*4882a593Smuzhiyun #define BADGE4_GPIO_BREQ_1111 GPIO_GPIO22 /* GPIO_TREQA */ 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define BADGE4_GPIO_TESTPT_J6 GPIO_GPIO23 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define BADGE4_GPIO_PCMEN5V GPIO_GPIO24 /* 5V power */ 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define BADGE4_GPIO_SA1111_NRST GPIO_GPIO25 /* SA-1111 nRESET */ 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define BADGE4_GPIO_TESTPT_J5 GPIO_GPIO26 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define BADGE4_GPIO_CLK_1111 GPIO_GPIO27 /* GPIO_32_768kHz */ 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* Interrupts on the BadgePAD 4 */ 58*4882a593Smuzhiyun #define BADGE4_IRQ_GPIO_SA1111 IRQ_GPIO0 /* SA-1111 interrupt */ 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* PCM5ENV Usage tracking */ 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define BADGE4_5V_PCMCIA_SOCK0 (1<<0) 64*4882a593Smuzhiyun #define BADGE4_5V_PCMCIA_SOCK1 (1<<1) 65*4882a593Smuzhiyun #define BADGE4_5V_PCMCIA_SOCK(n) (1<<(n)) 66*4882a593Smuzhiyun #define BADGE4_5V_USB (1<<2) 67*4882a593Smuzhiyun #define BADGE4_5V_INITIALLY (1<<3) 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 70*4882a593Smuzhiyun extern void badge4_set_5V(unsigned subsystem, int on); 71*4882a593Smuzhiyun #endif 72