1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * arch/arm/mach-sa1100/include/mach/assabet.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Created 2000/06/05 by Nicolas Pitre <nico@fluxnic.net> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * This file contains the hardware specific definitions for Assabet 8*4882a593Smuzhiyun * Only include this file from SA1100-specific files. 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * 2000/05/23 John Dorsey <john+@cs.cmu.edu> 11*4882a593Smuzhiyun * Definitions for Neponset added. 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun #ifndef __ASM_ARCH_ASSABET_H 14*4882a593Smuzhiyun #define __ASM_ARCH_ASSABET_H 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* System Configuration Register flags */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define ASSABET_SCR_SDRAM_LOW (1<<2) /* SDRAM size (low bit) */ 20*4882a593Smuzhiyun #define ASSABET_SCR_SDRAM_HIGH (1<<3) /* SDRAM size (high bit) */ 21*4882a593Smuzhiyun #define ASSABET_SCR_FLASH_LOW (1<<4) /* Flash size (low bit) */ 22*4882a593Smuzhiyun #define ASSABET_SCR_FLASH_HIGH (1<<5) /* Flash size (high bit) */ 23*4882a593Smuzhiyun #define ASSABET_SCR_GFX (1<<8) /* Graphics Accelerator (0 = present) */ 24*4882a593Smuzhiyun #define ASSABET_SCR_SA1111 (1<<9) /* Neponset (0 = present) */ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define ASSABET_SCR_INIT -1 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun extern unsigned long SCR_value; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #ifdef CONFIG_ASSABET_NEPONSET 31*4882a593Smuzhiyun #define machine_has_neponset() ((SCR_value & ASSABET_SCR_SA1111) == 0) 32*4882a593Smuzhiyun #else 33*4882a593Smuzhiyun #define machine_has_neponset() (0) 34*4882a593Smuzhiyun #endif 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* Board Control Register */ 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define ASSABET_BCR_BASE 0xf1000000 39*4882a593Smuzhiyun #define ASSABET_BCR (*(volatile unsigned int *)(ASSABET_BCR_BASE)) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define ASSABET_BCR_CF_PWR (1<<0) /* Compact Flash Power (1 = 3.3v, 0 = off) */ 42*4882a593Smuzhiyun #define ASSABET_BCR_CF_RST (1<<1) /* Compact Flash Reset (1 = power up reset) */ 43*4882a593Smuzhiyun #define ASSABET_BCR_NGFX_RST (1<<1) /* Graphics Accelerator Reset (0 = hold reset) */ 44*4882a593Smuzhiyun #define ASSABET_BCR_NCODEC_RST (1<<2) /* 0 = Holds UCB1300, ADI7171, and UDA1341 in reset */ 45*4882a593Smuzhiyun #define ASSABET_BCR_IRDA_FSEL (1<<3) /* IRDA Frequency select (0 = SIR, 1 = MIR/ FIR) */ 46*4882a593Smuzhiyun #define ASSABET_BCR_IRDA_MD0 (1<<4) /* Range/Power select */ 47*4882a593Smuzhiyun #define ASSABET_BCR_IRDA_MD1 (1<<5) /* Range/Power select */ 48*4882a593Smuzhiyun #define ASSABET_BCR_STEREO_LB (1<<6) /* Stereo Loopback */ 49*4882a593Smuzhiyun #define ASSABET_BCR_CF_BUS_OFF (1<<7) /* Compact Flash bus (0 = on, 1 = off (float)) */ 50*4882a593Smuzhiyun #define ASSABET_BCR_AUDIO_ON (1<<8) /* Audio power on */ 51*4882a593Smuzhiyun #define ASSABET_BCR_LIGHT_ON (1<<9) /* Backlight */ 52*4882a593Smuzhiyun #define ASSABET_BCR_LCD_12RGB (1<<10) /* 0 = 16RGB, 1 = 12RGB */ 53*4882a593Smuzhiyun #define ASSABET_BCR_LCD_ON (1<<11) /* LCD power on */ 54*4882a593Smuzhiyun #define ASSABET_BCR_RS232EN (1<<12) /* RS232 transceiver enable */ 55*4882a593Smuzhiyun #define ASSABET_BCR_LED_RED (1<<13) /* D9 (0 = on, 1 = off) */ 56*4882a593Smuzhiyun #define ASSABET_BCR_LED_GREEN (1<<14) /* D8 (0 = on, 1 = off) */ 57*4882a593Smuzhiyun #define ASSABET_BCR_VIB_ON (1<<15) /* Vibration motor (quiet alert) */ 58*4882a593Smuzhiyun #define ASSABET_BCR_COM_DTR (1<<16) /* COMport Data Terminal Ready */ 59*4882a593Smuzhiyun #define ASSABET_BCR_COM_RTS (1<<17) /* COMport Request To Send */ 60*4882a593Smuzhiyun #define ASSABET_BCR_RAD_WU (1<<18) /* Radio wake up interrupt */ 61*4882a593Smuzhiyun #define ASSABET_BCR_SMB_EN (1<<19) /* System management bus enable */ 62*4882a593Smuzhiyun #define ASSABET_BCR_TV_IR_DEC (1<<20) /* TV IR Decode Enable (not implemented) */ 63*4882a593Smuzhiyun #define ASSABET_BCR_QMUTE (1<<21) /* Quick Mute */ 64*4882a593Smuzhiyun #define ASSABET_BCR_RAD_ON (1<<22) /* Radio Power On */ 65*4882a593Smuzhiyun #define ASSABET_BCR_SPK_OFF (1<<23) /* 1 = Speaker amplifier power off */ 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #ifdef CONFIG_SA1100_ASSABET 68*4882a593Smuzhiyun extern void ASSABET_BCR_frob(unsigned int mask, unsigned int set); 69*4882a593Smuzhiyun #else 70*4882a593Smuzhiyun #define ASSABET_BCR_frob(x,y) do { } while (0) 71*4882a593Smuzhiyun #endif 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun extern void assabet_uda1341_reset(int set); 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define ASSABET_BCR_set(x) ASSABET_BCR_frob((x), (x)) 76*4882a593Smuzhiyun #define ASSABET_BCR_clear(x) ASSABET_BCR_frob((x), 0) 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define ASSABET_BSR_BASE 0xf1000000 79*4882a593Smuzhiyun #define ASSABET_BSR (*(volatile unsigned int*)(ASSABET_BSR_BASE)) 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define ASSABET_BSR_RS232_VALID (1 << 24) 82*4882a593Smuzhiyun #define ASSABET_BSR_COM_DCD (1 << 25) 83*4882a593Smuzhiyun #define ASSABET_BSR_COM_CTS (1 << 26) 84*4882a593Smuzhiyun #define ASSABET_BSR_COM_DSR (1 << 27) 85*4882a593Smuzhiyun #define ASSABET_BSR_RAD_CTS (1 << 28) 86*4882a593Smuzhiyun #define ASSABET_BSR_RAD_DSR (1 << 29) 87*4882a593Smuzhiyun #define ASSABET_BSR_RAD_DCD (1 << 30) 88*4882a593Smuzhiyun #define ASSABET_BSR_RAD_RI (1 << 31) 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* GPIOs (bitmasks) for which the generic definition doesn't say much */ 92*4882a593Smuzhiyun #define ASSABET_GPIO_RADIO_IRQ GPIO_GPIO (14) /* Radio interrupt request */ 93*4882a593Smuzhiyun #define ASSABET_GPIO_PS_MODE_SYNC GPIO_GPIO (16) /* Power supply mode/sync */ 94*4882a593Smuzhiyun #define ASSABET_GPIO_STEREO_64FS_CLK GPIO_GPIO (19) /* SSP UDA1341 clock input */ 95*4882a593Smuzhiyun #define ASSABET_GPIO_GFX_IRQ GPIO_GPIO (24) /* Graphics IRQ */ 96*4882a593Smuzhiyun #define ASSABET_GPIO_BATT_LOW GPIO_GPIO (26) /* Low battery */ 97*4882a593Smuzhiyun #define ASSABET_GPIO_RCLK GPIO_GPIO (26) /* CCLK/2 */ 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun #endif 100