1*4882a593Smuzhiyun/* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun/* linux/arch/arm/plat-s3c64xx/sleep.S 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright 2008 Openmoko, Inc. 5*4882a593Smuzhiyun * Copyright 2008 Simtec Electronics 6*4882a593Smuzhiyun * Ben Dooks <ben@simtec.co.uk> 7*4882a593Smuzhiyun * http://armlinux.simtec.co.uk/ 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * S3C64XX CPU sleep code 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun#include <linux/linkage.h> 13*4882a593Smuzhiyun#include <asm/assembler.h> 14*4882a593Smuzhiyun#include "map.h" 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun#undef S3C64XX_VA_GPIO 17*4882a593Smuzhiyun#define S3C64XX_VA_GPIO (0x0) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun#include "regs-gpio.h" 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun#define LL_UART (S3C_PA_UART + (0x400 * CONFIG_S3C_LOWLEVEL_UART_PORT)) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun .text 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* Sleep magic, the word before the resume entry point so that the 26*4882a593Smuzhiyun * bootloader can check for a resumeable image. */ 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun .word 0x2bedf00d 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* s3c_cpu_reusme 31*4882a593Smuzhiyun * 32*4882a593Smuzhiyun * This is the entry point, stored by whatever method the bootloader 33*4882a593Smuzhiyun * requires to get the kernel runnign again. This code expects to be 34*4882a593Smuzhiyun * entered with no caches live and the MMU disabled. It will then 35*4882a593Smuzhiyun * restore the MMU and other basic CP registers saved and restart 36*4882a593Smuzhiyun * the kernel C code to finish the resume code. 37*4882a593Smuzhiyun */ 38*4882a593Smuzhiyun 39*4882a593SmuzhiyunENTRY(s3c_cpu_resume) 40*4882a593Smuzhiyun msr cpsr_c, #PSR_I_BIT | PSR_F_BIT | SVC_MODE 41*4882a593Smuzhiyun ldr r2, =LL_UART /* for debug */ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun#define S3C64XX_GPNCON (S3C64XX_GPN_BASE + 0x00) 46*4882a593Smuzhiyun#define S3C64XX_GPNDAT (S3C64XX_GPN_BASE + 0x04) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun#define S3C64XX_GPN_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) 49*4882a593Smuzhiyun#define S3C64XX_GPN_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* Initialise the GPIO state if we are debugging via the SMDK LEDs, 52*4882a593Smuzhiyun * as the uboot version supplied resets these to inputs during the 53*4882a593Smuzhiyun * resume checks. 54*4882a593Smuzhiyun */ 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun ldr r3, =S3C64XX_PA_GPIO 57*4882a593Smuzhiyun ldr r0, [ r3, #S3C64XX_GPNCON ] 58*4882a593Smuzhiyun bic r0, r0, #(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) | \ 59*4882a593Smuzhiyun S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15)) 60*4882a593Smuzhiyun orr r0, r0, #(S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) | \ 61*4882a593Smuzhiyun S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15)) 62*4882a593Smuzhiyun str r0, [ r3, #S3C64XX_GPNCON ] 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun ldr r0, [ r3, #S3C64XX_GPNDAT ] 65*4882a593Smuzhiyun bic r0, r0, #0xf << 12 @ GPN12..15 66*4882a593Smuzhiyun orr r0, r0, #1 << 15 @ GPN15 67*4882a593Smuzhiyun str r0, [ r3, #S3C64XX_GPNDAT ] 68*4882a593Smuzhiyun#endif 69*4882a593Smuzhiyun b cpu_resume 70