1*4882a593Smuzhiyun/* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2004 Simtec Electronics 4*4882a593Smuzhiyun * Ben Dooks <ben@simtec.co.uk> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * S3C2410 Power Manager (Suspend-To-RAM) support 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Based on PXA/SA1100 sleep code by: 9*4882a593Smuzhiyun * Nicolas Pitre, (c) 2002 Monta Vista Software Inc 10*4882a593Smuzhiyun * Cliff Brake, (c) 2001 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun#include <linux/linkage.h> 14*4882a593Smuzhiyun#include <linux/serial_s3c.h> 15*4882a593Smuzhiyun#include <asm/assembler.h> 16*4882a593Smuzhiyun#include "map.h" 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun#include "regs-gpio.h" 19*4882a593Smuzhiyun#include "regs-clock.h" 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun/* 22*4882a593Smuzhiyun * S3C24XX_DEBUG_RESUME is dangerous if your bootloader does not 23*4882a593Smuzhiyun * reset the UART configuration, only enable if you really need this! 24*4882a593Smuzhiyun */ 25*4882a593Smuzhiyun//#define S3C24XX_DEBUG_RESUME 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun .text 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* sleep magic, to allow the bootloader to check for an valid 30*4882a593Smuzhiyun * image to resume to. Must be the first word before the 31*4882a593Smuzhiyun * s3c_cpu_resume entry. 32*4882a593Smuzhiyun */ 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun .word 0x2bedf00d 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* s3c_cpu_resume 37*4882a593Smuzhiyun * 38*4882a593Smuzhiyun * resume code entry for bootloader to call 39*4882a593Smuzhiyun */ 40*4882a593Smuzhiyun 41*4882a593SmuzhiyunENTRY(s3c_cpu_resume) 42*4882a593Smuzhiyun mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE 43*4882a593Smuzhiyun msr cpsr_c, r0 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun @@ load UART to allow us to print the two characters for 46*4882a593Smuzhiyun @@ resume debug 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun mov r2, #S3C24XX_PA_UART & 0xff000000 49*4882a593Smuzhiyun orr r2, r2, #S3C24XX_PA_UART & 0xff000 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun#if 0 52*4882a593Smuzhiyun /* SMDK2440 LED set */ 53*4882a593Smuzhiyun mov r14, #S3C24XX_PA_GPIO 54*4882a593Smuzhiyun ldr r12, [ r14, #0x54 ] 55*4882a593Smuzhiyun bic r12, r12, #3<<4 56*4882a593Smuzhiyun orr r12, r12, #1<<7 57*4882a593Smuzhiyun str r12, [ r14, #0x54 ] 58*4882a593Smuzhiyun#endif 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun#ifdef S3C24XX_DEBUG_RESUME 61*4882a593Smuzhiyun mov r3, #'L' 62*4882a593Smuzhiyun strb r3, [ r2, #S3C2410_UTXH ] 63*4882a593Smuzhiyun1001: 64*4882a593Smuzhiyun ldrb r14, [ r3, #S3C2410_UTRSTAT ] 65*4882a593Smuzhiyun tst r14, #S3C2410_UTRSTAT_TXE 66*4882a593Smuzhiyun beq 1001b 67*4882a593Smuzhiyun#endif /* S3C24XX_DEBUG_RESUME */ 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun b cpu_resume 70