1*4882a593Smuzhiyun/* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2004 Simtec Electronics 4*4882a593Smuzhiyun * Ben Dooks <ben@simtec.co.uk> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * S3C2410 Power Manager (Suspend-To-RAM) support 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Based on PXA/SA1100 sleep code by: 9*4882a593Smuzhiyun * Nicolas Pitre, (c) 2002 Monta Vista Software Inc 10*4882a593Smuzhiyun * Cliff Brake, (c) 2001 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun#include <linux/linkage.h> 14*4882a593Smuzhiyun#include <linux/serial_s3c.h> 15*4882a593Smuzhiyun#include <asm/assembler.h> 16*4882a593Smuzhiyun#include "map.h" 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun#include "regs-gpio.h" 19*4882a593Smuzhiyun#include "regs-clock.h" 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun#include "regs-mem-s3c24xx.h" 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* s3c2410_cpu_suspend 24*4882a593Smuzhiyun * 25*4882a593Smuzhiyun * put the cpu into sleep mode 26*4882a593Smuzhiyun */ 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunENTRY(s3c2410_cpu_suspend) 29*4882a593Smuzhiyun @@ prepare cpu to sleep 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun ldr r4, =S3C2410_REFRESH 32*4882a593Smuzhiyun ldr r5, =S3C24XX_MISCCR 33*4882a593Smuzhiyun ldr r6, =S3C2410_CLKCON 34*4882a593Smuzhiyun ldr r7, [r4] @ get REFRESH (and ensure in TLB) 35*4882a593Smuzhiyun ldr r8, [r5] @ get MISCCR (and ensure in TLB) 36*4882a593Smuzhiyun ldr r9, [r6] @ get CLKCON (and ensure in TLB) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun orr r7, r7, #S3C2410_REFRESH_SELF @ SDRAM sleep command 39*4882a593Smuzhiyun orr r8, r8, #S3C2410_MISCCR_SDSLEEP @ SDRAM power-down signals 40*4882a593Smuzhiyun orr r9, r9, #S3C2410_CLKCON_POWER @ power down command 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun teq pc, #0 @ first as a trial-run to load cache 43*4882a593Smuzhiyun bl s3c2410_do_sleep 44*4882a593Smuzhiyun teq r0, r0 @ now do it for real 45*4882a593Smuzhiyun b s3c2410_do_sleep @ 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun @@ align next bit of code to cache line 48*4882a593Smuzhiyun .align 5 49*4882a593Smuzhiyuns3c2410_do_sleep: 50*4882a593Smuzhiyun streq r7, [r4] @ SDRAM sleep command 51*4882a593Smuzhiyun streq r8, [r5] @ SDRAM power-down config 52*4882a593Smuzhiyun streq r9, [r6] @ CPU sleep 53*4882a593Smuzhiyun1: beq 1b 54*4882a593Smuzhiyun ret lr 55