1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // Copyright (c) 2010 Samsung Electronics Co., Ltd.
4*4882a593Smuzhiyun // http://www.samsung.com/
5*4882a593Smuzhiyun //
6*4882a593Smuzhiyun // S3C64XX setup information for IDE
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/kernel.h>
9*4882a593Smuzhiyun #include <linux/gpio.h>
10*4882a593Smuzhiyun #include <linux/io.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/platform_data/ata-samsung_cf.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include "map.h"
15*4882a593Smuzhiyun #include "regs-clock.h"
16*4882a593Smuzhiyun #include "gpio-cfg.h"
17*4882a593Smuzhiyun #include "gpio-samsung.h"
18*4882a593Smuzhiyun
s3c64xx_ide_setup_gpio(void)19*4882a593Smuzhiyun void s3c64xx_ide_setup_gpio(void)
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun u32 reg;
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun reg = readl(S3C_MEM_SYS_CFG) & (~0x3f);
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /* Independent CF interface, CF chip select configuration */
26*4882a593Smuzhiyun writel(reg | MEM_SYS_CFG_INDEP_CF |
27*4882a593Smuzhiyun MEM_SYS_CFG_EBI_FIX_PRI_CFCON, S3C_MEM_SYS_CFG);
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun s3c_gpio_cfgpin(S3C64XX_GPB(4), S3C_GPIO_SFN(4));
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /* Set XhiDATA[15:0] pins as CF Data[15:0] */
32*4882a593Smuzhiyun s3c_gpio_cfgpin_range(S3C64XX_GPK(0), 16, S3C_GPIO_SFN(5));
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /* Set XhiADDR[2:0] pins as CF ADDR[2:0] */
35*4882a593Smuzhiyun s3c_gpio_cfgpin_range(S3C64XX_GPL(0), 3, S3C_GPIO_SFN(6));
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /* Set Xhi ctrl pins as CF ctrl pins(IORDY, IOWR, IORD, CE[0:1]) */
38*4882a593Smuzhiyun s3c_gpio_cfgpin(S3C64XX_GPM(5), S3C_GPIO_SFN(1));
39*4882a593Smuzhiyun s3c_gpio_cfgpin_range(S3C64XX_GPM(0), 5, S3C_GPIO_SFN(6));
40*4882a593Smuzhiyun }
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