1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2011 Samsung Electronics Co., Ltd. 4*4882a593Smuzhiyun * http://www.samsung.com 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright 2008 Openmoko, Inc. 7*4882a593Smuzhiyun * Copyright 2008 Simtec Electronics 8*4882a593Smuzhiyun * Ben Dooks <ben@simtec.co.uk> 9*4882a593Smuzhiyun * http://armlinux.simtec.co.uk/ 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * Common Header for S3C64XX machines 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifndef __ARCH_ARM_MACH_S3C64XX_COMMON_H 15*4882a593Smuzhiyun #define __ARCH_ARM_MACH_S3C64XX_COMMON_H 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #include <linux/reboot.h> 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun void s3c64xx_init_irq(u32 vic0, u32 vic1); 20*4882a593Smuzhiyun void s3c64xx_init_io(struct map_desc *mach_desc, int size); 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun struct device_node; 23*4882a593Smuzhiyun void s3c64xx_set_xtal_freq(unsigned long freq); 24*4882a593Smuzhiyun void s3c64xx_set_xusbxti_freq(unsigned long freq); 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #ifdef CONFIG_CPU_S3C6400 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun extern int s3c6400_init(void); 29*4882a593Smuzhiyun extern void s3c6400_init_irq(void); 30*4882a593Smuzhiyun extern void s3c6400_map_io(void); 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #else 33*4882a593Smuzhiyun #define s3c6400_map_io NULL 34*4882a593Smuzhiyun #define s3c6400_init NULL 35*4882a593Smuzhiyun #endif 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #ifdef CONFIG_CPU_S3C6410 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun extern int s3c6410_init(void); 40*4882a593Smuzhiyun extern void s3c6410_init_irq(void); 41*4882a593Smuzhiyun extern void s3c6410_map_io(void); 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #else 44*4882a593Smuzhiyun #define s3c6410_map_io NULL 45*4882a593Smuzhiyun #define s3c6410_init NULL 46*4882a593Smuzhiyun #endif 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #ifdef CONFIG_S3C64XX_PL080 49*4882a593Smuzhiyun extern struct pl08x_platform_data s3c64xx_dma0_plat_data; 50*4882a593Smuzhiyun extern struct pl08x_platform_data s3c64xx_dma1_plat_data; 51*4882a593Smuzhiyun #endif 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* Samsung HR-Timer Clock mode */ 54*4882a593Smuzhiyun enum s3c64xx_timer_mode { 55*4882a593Smuzhiyun S3C64XX_PWM0, 56*4882a593Smuzhiyun S3C64XX_PWM1, 57*4882a593Smuzhiyun S3C64XX_PWM2, 58*4882a593Smuzhiyun S3C64XX_PWM3, 59*4882a593Smuzhiyun S3C64XX_PWM4, 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun extern void __init s3c64xx_set_timer_source(enum s3c64xx_timer_mode event, 63*4882a593Smuzhiyun enum s3c64xx_timer_mode source); 64*4882a593Smuzhiyun extern void __init s3c64xx_timer_init(void); 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #endif /* __ARCH_ARM_MACH_S3C64XX_COMMON_H */ 67