1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2008 Openmoko, Inc. 4*4882a593Smuzhiyun * Copyright 2008 Simtec Electronics 5*4882a593Smuzhiyun * http://armlinux.simtec.co.uk/ 6*4882a593Smuzhiyun * Ben Dooks <ben@simtec.co.uk> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * S3C - USB2.0 Highspeed/OtG device PHY registers 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* Note, this is a separate header file as some of the clock framework 12*4882a593Smuzhiyun * needs to touch this if the clk_48m is used as the USB OHCI or other 13*4882a593Smuzhiyun * peripheral source. 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #ifndef __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H 17*4882a593Smuzhiyun #define __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H __FILE__ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* S3C64XX_PA_USB_HSPHY */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define S3C_HSOTG_PHYREG(x) ((x) + S3C_VA_USB_HSPHY) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define S3C_PHYPWR S3C_HSOTG_PHYREG(0x00) 24*4882a593Smuzhiyun #define S3C_PHYPWR_NORMAL_MASK (0x19 << 0) 25*4882a593Smuzhiyun #define S3C_PHYPWR_OTG_DISABLE (1 << 4) 26*4882a593Smuzhiyun #define S3C_PHYPWR_ANALOG_POWERDOWN (1 << 3) 27*4882a593Smuzhiyun #define SRC_PHYPWR_FORCE_SUSPEND (1 << 1) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define S3C_PHYCLK S3C_HSOTG_PHYREG(0x04) 30*4882a593Smuzhiyun #define S3C_PHYCLK_MODE_USB11 (1 << 6) 31*4882a593Smuzhiyun #define S3C_PHYCLK_EXT_OSC (1 << 5) 32*4882a593Smuzhiyun #define S3C_PHYCLK_CLK_FORCE (1 << 4) 33*4882a593Smuzhiyun #define S3C_PHYCLK_ID_PULL (1 << 2) 34*4882a593Smuzhiyun #define S3C_PHYCLK_CLKSEL_MASK (0x3 << 0) 35*4882a593Smuzhiyun #define S3C_PHYCLK_CLKSEL_SHIFT (0) 36*4882a593Smuzhiyun #define S3C_PHYCLK_CLKSEL_48M (0x0 << 0) 37*4882a593Smuzhiyun #define S3C_PHYCLK_CLKSEL_12M (0x2 << 0) 38*4882a593Smuzhiyun #define S3C_PHYCLK_CLKSEL_24M (0x3 << 0) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define S3C_RSTCON S3C_HSOTG_PHYREG(0x08) 41*4882a593Smuzhiyun #define S3C_RSTCON_PHYCLK (1 << 2) 42*4882a593Smuzhiyun #define S3C_RSTCON_HCLK (1 << 1) 43*4882a593Smuzhiyun #define S3C_RSTCON_PHY (1 << 0) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define S3C_PHYTUNE S3C_HSOTG_PHYREG(0x20) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #endif /* __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H */ 48