1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2009 Andy Green <andy@warmcat.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * S3C64XX SROM definitions 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __MACH_S3C64XX_REGS_SROM_H 9*4882a593Smuzhiyun #define __MACH_S3C64XX_REGS_SROM_H __FILE__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define S3C64XX_SROMREG(x) (S3C_VA_MEM + (x)) 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define S3C64XX_SROM_BW S3C64XX_SROMREG(0) 14*4882a593Smuzhiyun #define S3C64XX_SROM_BC0 S3C64XX_SROMREG(4) 15*4882a593Smuzhiyun #define S3C64XX_SROM_BC1 S3C64XX_SROMREG(8) 16*4882a593Smuzhiyun #define S3C64XX_SROM_BC2 S3C64XX_SROMREG(0xc) 17*4882a593Smuzhiyun #define S3C64XX_SROM_BC3 S3C64XX_SROMREG(0x10) 18*4882a593Smuzhiyun #define S3C64XX_SROM_BC4 S3C64XX_SROMREG(0x14) 19*4882a593Smuzhiyun #define S3C64XX_SROM_BC5 S3C64XX_SROMREG(0x18) 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* 22*4882a593Smuzhiyun * one register BW holds 5 x 4-bit packed settings for NCS0 - NCS4 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define S3C64XX_SROM_BW__DATAWIDTH__SHIFT 0 26*4882a593Smuzhiyun #define S3C64XX_SROM_BW__WAITENABLE__SHIFT 2 27*4882a593Smuzhiyun #define S3C64XX_SROM_BW__BYTEENABLE__SHIFT 3 28*4882a593Smuzhiyun #define S3C64XX_SROM_BW__CS_MASK 0xf 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define S3C64XX_SROM_BW__NCS0__SHIFT 0 31*4882a593Smuzhiyun #define S3C64XX_SROM_BW__NCS1__SHIFT 4 32*4882a593Smuzhiyun #define S3C64XX_SROM_BW__NCS2__SHIFT 8 33*4882a593Smuzhiyun #define S3C64XX_SROM_BW__NCS3__SHIFT 0xc 34*4882a593Smuzhiyun #define S3C64XX_SROM_BW__NCS4__SHIFT 0x10 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* 37*4882a593Smuzhiyun * applies to same to BCS0 - BCS4 38*4882a593Smuzhiyun */ 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define S3C64XX_SROM_BCX__PMC__SHIFT 0 41*4882a593Smuzhiyun #define S3C64XX_SROM_BCX__PMC__MASK 3 42*4882a593Smuzhiyun #define S3C64XX_SROM_BCX__TACP__SHIFT 4 43*4882a593Smuzhiyun #define S3C64XX_SROM_BCX__TACP__MASK 0xf 44*4882a593Smuzhiyun #define S3C64XX_SROM_BCX__TCAH__SHIFT 8 45*4882a593Smuzhiyun #define S3C64XX_SROM_BCX__TCAH__MASK 0xf 46*4882a593Smuzhiyun #define S3C64XX_SROM_BCX__TCOH__SHIFT 12 47*4882a593Smuzhiyun #define S3C64XX_SROM_BCX__TCOH__MASK 0xf 48*4882a593Smuzhiyun #define S3C64XX_SROM_BCX__TACC__SHIFT 16 49*4882a593Smuzhiyun #define S3C64XX_SROM_BCX__TACC__MASK 0x1f 50*4882a593Smuzhiyun #define S3C64XX_SROM_BCX__TCOS__SHIFT 24 51*4882a593Smuzhiyun #define S3C64XX_SROM_BCX__TCOS__MASK 0xf 52*4882a593Smuzhiyun #define S3C64XX_SROM_BCX__TACS__SHIFT 28 53*4882a593Smuzhiyun #define S3C64XX_SROM_BCX__TACS__MASK 0xf 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #endif /* __MACH_S3C64XX_REGS_SROM_H */ 56