1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk> 4*4882a593Smuzhiyun * http://www.simtec.co.uk/products/SWLINUX/ 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * S3C2410 Memory Control register definitions 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H 10*4882a593Smuzhiyun #define __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H __FILE__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include "map-s3c.h" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define S3C2410_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x)) 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define S3C2410_BWSCON S3C2410_MEMREG(0x00) 17*4882a593Smuzhiyun #define S3C2410_BANKCON0 S3C2410_MEMREG(0x04) 18*4882a593Smuzhiyun #define S3C2410_BANKCON1 S3C2410_MEMREG(0x08) 19*4882a593Smuzhiyun #define S3C2410_BANKCON2 S3C2410_MEMREG(0x0C) 20*4882a593Smuzhiyun #define S3C2410_BANKCON3 S3C2410_MEMREG(0x10) 21*4882a593Smuzhiyun #define S3C2410_BANKCON4 S3C2410_MEMREG(0x14) 22*4882a593Smuzhiyun #define S3C2410_BANKCON5 S3C2410_MEMREG(0x18) 23*4882a593Smuzhiyun #define S3C2410_BANKCON6 S3C2410_MEMREG(0x1C) 24*4882a593Smuzhiyun #define S3C2410_BANKCON7 S3C2410_MEMREG(0x20) 25*4882a593Smuzhiyun #define S3C2410_REFRESH S3C2410_MEMREG(0x24) 26*4882a593Smuzhiyun #define S3C2410_BANKSIZE S3C2410_MEMREG(0x28) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define S3C2410_BWSCON_ST1 (1 << 7) 29*4882a593Smuzhiyun #define S3C2410_BWSCON_ST2 (1 << 11) 30*4882a593Smuzhiyun #define S3C2410_BWSCON_ST3 (1 << 15) 31*4882a593Smuzhiyun #define S3C2410_BWSCON_ST4 (1 << 19) 32*4882a593Smuzhiyun #define S3C2410_BWSCON_ST5 (1 << 23) 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define S3C2410_BWSCON_GET(_bwscon, _bank) (((_bwscon) >> ((_bank) * 4)) & 0xf) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define S3C2410_BWSCON_WS (1 << 2) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define S3C2410_BANKCON_PMC16 (0x3) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define S3C2410_BANKCON_Tacp_SHIFT (2) 41*4882a593Smuzhiyun #define S3C2410_BANKCON_Tcah_SHIFT (4) 42*4882a593Smuzhiyun #define S3C2410_BANKCON_Tcoh_SHIFT (6) 43*4882a593Smuzhiyun #define S3C2410_BANKCON_Tacc_SHIFT (8) 44*4882a593Smuzhiyun #define S3C2410_BANKCON_Tcos_SHIFT (11) 45*4882a593Smuzhiyun #define S3C2410_BANKCON_Tacs_SHIFT (13) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define S3C2410_BANKCON_SDRAM (0x3 << 15) 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define S3C2410_REFRESH_SELF (1 << 22) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define S3C2410_BANKSIZE_MASK (0x7 << 0) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #endif /* __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H */ 54