1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> 4*4882a593Smuzhiyun * http://www.simtec.co.uk/products/SWLINUX/ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef ___ASM_ARCH_REGS_IRQ_H 9*4882a593Smuzhiyun #define ___ASM_ARCH_REGS_IRQ_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include "map-s3c.h" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* interrupt controller */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define S3C2410_IRQREG(x) ((x) + S3C24XX_VA_IRQ) 16*4882a593Smuzhiyun #define S3C2410_EINTREG(x) ((x) + S3C24XX_VA_GPIO) 17*4882a593Smuzhiyun #define S3C24XX_EINTREG(x) ((x) + S3C24XX_VA_GPIO2) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define S3C2410_SRCPND S3C2410_IRQREG(0x000) 20*4882a593Smuzhiyun #define S3C2410_INTMOD S3C2410_IRQREG(0x004) 21*4882a593Smuzhiyun #define S3C2410_INTMSK S3C2410_IRQREG(0x008) 22*4882a593Smuzhiyun #define S3C2410_PRIORITY S3C2410_IRQREG(0x00C) 23*4882a593Smuzhiyun #define S3C2410_INTPND S3C2410_IRQREG(0x010) 24*4882a593Smuzhiyun #define S3C2410_INTOFFSET S3C2410_IRQREG(0x014) 25*4882a593Smuzhiyun #define S3C2410_SUBSRCPND S3C2410_IRQREG(0x018) 26*4882a593Smuzhiyun #define S3C2410_INTSUBMSK S3C2410_IRQREG(0x01C) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define S3C2416_PRIORITY_MODE1 S3C2410_IRQREG(0x030) 29*4882a593Smuzhiyun #define S3C2416_PRIORITY_UPDATE1 S3C2410_IRQREG(0x034) 30*4882a593Smuzhiyun #define S3C2416_SRCPND2 S3C2410_IRQREG(0x040) 31*4882a593Smuzhiyun #define S3C2416_INTMOD2 S3C2410_IRQREG(0x044) 32*4882a593Smuzhiyun #define S3C2416_INTMSK2 S3C2410_IRQREG(0x048) 33*4882a593Smuzhiyun #define S3C2416_INTPND2 S3C2410_IRQREG(0x050) 34*4882a593Smuzhiyun #define S3C2416_INTOFFSET2 S3C2410_IRQREG(0x054) 35*4882a593Smuzhiyun #define S3C2416_PRIORITY_MODE2 S3C2410_IRQREG(0x070) 36*4882a593Smuzhiyun #define S3C2416_PRIORITY_UPDATE2 S3C2410_IRQREG(0x074) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* mask: 0=enable, 1=disable 39*4882a593Smuzhiyun * 1 bit EINT, 4=EINT4, 23=EINT23 40*4882a593Smuzhiyun * EINT0,1,2,3 are not handled here. 41*4882a593Smuzhiyun */ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define S3C2410_EINTMASK S3C2410_EINTREG(0x0A4) 44*4882a593Smuzhiyun #define S3C2410_EINTPEND S3C2410_EINTREG(0X0A8) 45*4882a593Smuzhiyun #define S3C2412_EINTMASK S3C2410_EINTREG(0x0B4) 46*4882a593Smuzhiyun #define S3C2412_EINTPEND S3C2410_EINTREG(0X0B8) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define S3C24XX_EINTMASK S3C24XX_EINTREG(0x0A4) 49*4882a593Smuzhiyun #define S3C24XX_EINTPEND S3C24XX_EINTREG(0X0A8) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #endif /* ___ASM_ARCH_REGS_IRQ_H */ 52